Week 2 Activities

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Tips:

	Use a 'parameter' definition for numerical constants that must be changed between simulation and synthesis, e.g., clock divider max value. Take a look at ifdef.v to learn a simple technique to make this happen automatically.
	See comments.v to learn how to automatically embed comments in your waveform display.
	The analog hardware behavior as seen by the digital controller can be emulated in a stand-alone 'always' block. From the controller's point of view, you apply a 7-bit value to the analog hardware and you get a 1-bit result after about 5 microseconds, so the analog hardware can be viewed as a sort of combinational (memoryless) circuit. You can emulate the analog input voltage with 7-bit value (declared as 'reg') that can be changed in the 'initial' block at the beginning of the next conversion cycle.
	Use 'wait' to create a delay that depends on a signal. For example, if your system has a signal called "Done" to indicate that the conversion cycle has completed, then use 'wait (Done==1)' as a delay in the same way that you have used a fixed delay such as '#10000'. The major advantage with the 'wait' technique is that you don't have to pre-calculate how long it will take for your device-under-test to complete an operation before you apply the next input stimulus.
	Do not rely on the 'Default' waveforms group to properly save your waveforms list. Instead, right-click and select "New Group" to create your own waveform group. Use right-click followed by "Reload Group" to recover it if it does not automatically reload. Apparently there is no "Save Group" option, but you will be prompted to save the group when you close the 'Analyzer' window.

Activities:

Refresh your memory about the Week 2 Deliverables and the testbench-related section of the Design Requirements.

Critical: Read (several times!) the ECE333 Design Rules document. When you adhere to the design rules, you are much less likely to spend a lot of time trying to understand why the synthesis tool does not like your design! It is quite easy to create designs that simulate successfully, even to the point of producing proper functional behavior, but that fail to synthesize properly. You may wish to review the Troubleshooting Tips document at this time to gain an idea of what can go wrong when the design rules are ignored.

Your goal at the end of Week 2 is to convince yourself and the instructor that your circuit works correctly in simulation, first at the individual module level, and then at the overall system level.

Implement the controller as a single module, and implement the datapath as one or more modules. Create a testbench for each module, and perform functional verification independently for each module. Produce annotated waveform plots for each of your modules. Do not proceed with integrating the modules together until you are convinced that each module works properly on its own!

Once you have individually verified each module in your system, create a top-level module to integrate the low-level modules into a single system. Prepare simulation waveform plots for the following time ranges (fit each plot type to a single page):

Two consecutive conversion cycles for two different analog voltage values
Beginning of a conversion cycle (showing transition of "Hold" from asserted level to deasserted level)
End of a conversion cycle

Each waveform plot should order the signals as follows (insert blank lines between related groups using right-click followed by "Add Blank Line"):

Clock, reset, comment
Primary inputs (inputs that originate outside Verilog module)
Primary outputs (outputs that are used by devices outside the Verilog module)
State of controller FSM
Control signals (from controller to datapath)
Condition signals (from datapath to controller)
Datapath devices (outputs of shift registers, counters, etc. that are internal to datapath but are nevertheless critical outputs to observe)

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Last updated: 03/10/05.