Resources

NOTE: Please go to PLD Oasis if you are looking for documentation and resources related to the Digilent FPGA boards, Xilinx software, and Verilog.

	ABEL-HDL Primer
	PLD Design Flow: GAL, ABEL
	ispLEVER 1.0 Starter Kit -- You can download this kit and install it on your own computer. The B-200 computers run the full version of ispLEVER.

PLD Design Flow: GAL, Verilog

	ispLEVER 1.0 Starter Kit
	Simplified schematic and ribbon cable pinouts (this is the primary reference)
	Full schematic

	Concept to FPGA: Step-by-Step Instructions
	XS-40 User's Manual
	About the programmable oscillator
	Location of Vdd and ground pins
	XSTOOLS software
	alive.bit tests FPGA and LED (source: alive.v and alive.ucf)

	Gradual Introduction to Verilog: Combinational and Sequential
	On-line Verilog HDL Quick Reference Guide by Stuart Sutherland
	v2html - Verilog-to-HTML converter
	FPGA System Design with Verilog: Workshop materials
	Verilog Template Maker
	Verilog examples [more complete at PLD Oasis]
	Reference design

	Obtaining hardcopy of MSO screen
	Obtaining "correct" front panel display for high-impedance loads

Design Project Tips

	Schematic and design equations
	555 Timer Design Tool: On-line Java applet to choose component values (handles standard component values nicely)

Transmission Line Effects on a Bus (Java applet)

PSpice demos (schematic files)

	Time domain
	Frequency domain

Grid paper for drawing timing diagrams (portrait or landscape)

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Last updated: 03/10/05.