The overall system must:

1. Accept input analog voltage in the range zero to five volts
2. Continually produce digital measurements ("conversion cycles") at the rate of 100 (±10%) Hz.
3. Produce a digital measurement with seven-bit resolution at the end of a conversion cycle that remains constant during the subsequent conversion cycle
4. Produce a digital value of zero for Vin = 0 volts (slight offsets are permissible)
5. Produce a digital value of 7F hexadecimal for Vin = 5 volts (slight offsets are permissible)
6. Include a "Pause" input (active high) that causes the system to complete the current conversion cycle, then wait until "Pause" is de-asserted before resuming conversion cycles
7. Provide the following primary outputs: (a) digital primary measurement (seven bits), (b) digital value of the current controlled voltage Vc (seven bits), and (c) an active-low status signal pulse of one state machine cycle in duration indicating a conversion cycle has just completed
8. Display a voltage level indicator on the XS40 seven-segment LED that displays the value of the most significant three bits of the digital measurement (must be a graphic indicator, not a numerical value).
9. Be demonstrated using a variable-voltage source as input, with the MSO displaying analog voltages Vin and Vc and all digital signals listed in (7) above as well as the analog comparator output

The digital controller must:

1. Be implemented using XS40 FPGA board
2. Be described in Verilog
3. Adhere to all ECE333 Design Rules for digital circuits
4. Use controller-datapath architecture, where the controller is implemented by a finite state machine
5. Use a minimum of three Verilog modules: a top-level module, a module for the controller, and one or more modules for the datapath
6. Use synchronizer for each asynchronous input
7. Be functionally verified in simulation using testbench methodology; a distinct testbench must be created for each module in the system, and the modules must be verified as stand-alone modules before integrating together in the top-level module
8. Use the 12 MHz oscillator on the XS40 board as the master clock

The testbench must:

1. Create comments that automatically appear in the waveform display to describe the current test procedure
2. Generate text labels to interpret the state code of the controller finite state machine
3. Emulate the behavior of the voltage comparator in a separate 'always' block

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