Your primary goal at the completion of this first week of the project is
to complete the conceptual design for your ADC system. You should not touch
your computer CAD tools during this phase of the design!
You should work with your lab partner to work out the details of the first
three major bullet points of the deliverables below. You may also work with your
lab partner to discuss issues and to brainstorm ideas about both ADC types. Once
you have decided which specific ADC you will implement, however, you must work
independently on your design to complete the remaining deliverables for this and
subsequent weeks.
You are to produce the following deliverables this week:
 | Symbol drawing for entire system
 | draw one block (rectangle) that represents the entire device |
| draw and label primary inputs on left side of block |
| draw and label primary outputs on right side of block |
|
| Block diagram for entire system
| show all major components in the entire system |
| show register-level detail for the digital system implemented by the
FPGA (use single blocks to represent the controller and datapath; details of
these elements will be shown in a separate diagram) |
| show specific interconnections between all devices |
| show FPGA boundary |
| show XS40 board boundary |
| hint: you will know that you have drawn a proper diagram when all
wires or buses begin at one block and end at another block; there must be no
"dangling" wires anywhere on the diagram |
|
| Symbol drawing for digital system
| draw one block (rectangle) that represents the digital system
implemented by the FPGA |
| draw and label primary inputs on left side of block |
| draw and label primary outputs on right side of block |
|
| State transition diagram for controller
| show states |
| use state names that are descriptive of the activity performed in each
state |
| make a table to indicate primary inputs, primary outputs, control points
(to datapath), and condition (status) signals (from datapath) |
| indicate which state is entered when the asynchronous master reset is
asserted |
|
| Register-level block diagram for datapath
| indicate control points (from controller) and condition signals (to
controller) |
| indicate the behavior desired from control inputs on the devices |
|
| Timing diagram
| controller: show state, external inputs, condition signals from datapath,
control signals to datapath |
| datapath: show outputs of datapath devices |
| overall system: show all inputs and outputs |
| include annotations and other notes to clearly explain causal
relationships between signals |
|
| Test plan for finished system
| state the procedures you will use to show that your finished product
meets all design requirements |
| state the procedures you will use to test the performance of your
finished ADC |
| remember that you are designing a measurement device, so consider what
you need to do to determine how well your measurement device works |
|
| Written commentary to explain how your system works |
