 Day |
Date |
Topic |
Reading |
| 1-1 |
M |
Dec 2 |
Course overview |
Ch 1 |
Review of digital logic concepts
|
| 1-2 |
T |
3 |
Combinational circuits |
Ch 5, 6 |
| 1-3 |
R |
5 |
Sequential circuits, finite state machines (FSMs) |
Ch 7-9 |
System design principles
|
| 2-1 |
M |
9 |
Handshaking between FSMs; Combinational ABEL |
Ch 4.6 and/or
ABEL-HDL Primer |
| 2-2 |
T |
10 |
Asynchronous inputs |
Ch 8.9.1 - 8.9.4 |
| 2-3 |
R |
12 |
Data path / controller partition; Sequential ABEL |
Ch 8.7 |
| 3-1 |
M |
16 |
Design example |
|
| 3-2 |
T |
17 |
Exam 1 |
|
Hardware description language techniques
|
| 3-3 |
R |
19 |
Verilog HDL |
Ch 4.7.1 |
| 4-1 |
M |
Jan 6 |
Combinational circuits |
Gradual Introduction to Verilog: Combinational |
| 4-2 |
T |
7 |
Simulation techniques for combinational circuits; examples |
|
| 4-3 |
R |
9 |
Sequential circuits |
Gradual Introduction to Verilog: Sequential |
| 5-1 |
M |
13 |
Simulation techniques for sequential circuits |
|
| 5-2 |
T |
14 |
Finite state machines,
multi-module systems |
|
| 5-3 |
R |
16 |
Datapath / controller example |
|
| 6-1 |
M |
20 |
Datapath / controller example |
|
| 6-2 |
T |
21 |
Exam 2 |
|
Analog realities
|
| 6-3 |
R |
23 |
CMOS logic |
Ch 3.1-3 |
| 7-1 |
M |
27 |
Transistor-level gates |
Ch 3.1-3 |
| 7-2 |
T |
28 |
Static (DC) electrical behavior, noise margin |
Ch 3.4-5 |
| 7-3 |
R |
30 |
Dynamic (AC) electrical behavior |
Ch 3.6 |
| 8-1 |
M |
Feb 3 |
I/O structures |
Ch 3.7 |
| 8-2 |
T |
4 |
I/O structures |
Ch 3.7 |
| 8-3 |
R |
6 |
EMC and signal integrity |
Review
Selected EMC and Signal
Integrity Resources |
| 9-1 |
M |
10 |
Transmission line effects |
Ch 11.4 and
Why Digital Engineers
Don't Believe in EMC |
| 9-2 |
T |
11 |
Design for T-line effects |
|
Digital devices
|
| 9-3 |
R |
13 |
Simple programmable logic devices (PLDs) |
Ch 5.3, 8.3 |
| 10-1 |
M |
17 |
Memory (ROM, RAM) |
Ch 10.1-4 |
| 10-2 |
T |
18 |
Complex PLDs and field-programmable gate arrays (FPGAs) |
Ch 10.5-6 |
| 10-3 |
R |
20 |
Applications |
|
finals
week |
|
|
Exam 3 |
|
