Timeline and Deliverables

You will need to produce a set of "deliverables" in your lab notebook by the end of each lab period for each of the three weeks of the project:

First week: Conceptual design and detailed design documents

	Symbol drawing for entire system
	Block diagram for entire system
	Symbol drawing for digital system
	State transition diagram for controller
	Register-level block diagram for datapath
	Timing diagram
	Test plan for finished system
	Written commentary to explain how your system works

Second week: Functional verification

	Synthesizable circuit descriptions (Verilog), one file for each module
	Testbenches (Verilog), one file for each module
	Waveform plots with annotations to interpret the results; includes simulation of the entire design as well as individual test results for each low-level module
	Written commentary to explain your test procedures and results

Third week: Hardware implementation

	Performance evaluation results (use your test plan)
	Demonstration for instructor
	Written commentary to explain your test procedures and results

A formal design project report detailing your design process and performance results will be due at the conclusion of the design project.

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Last updated: 03/10/05.