What to Do:

How to Do It:

Create Conceptual Design:

Draw I/O block diagram of your circuit, i.e., draw a rectangle with pins sticking out, and write a name for each pin (signal).

Use a piece of paper, and a pen or pencil :-)

You will find it helpful to clarify some basic details before you jump in with the computer tools.

Draw diagram of your circuit components and their interconnections.

See above.

The diagram will help you visualize the hardware when you write your circuit descriptions.

Enter Your Design:

Start ispLEVER

In Windows, do Start | Programs | Lattice Semiconductor | ispLEVER

Start a new project in ispLEVER

Select “File | New Project”

Enter a name for your project. It is recommended that you also create a new folder for your project, since the software will generate many files for your single project.

Do not use any special characters in your project name or folder name. In particular, do not use spaces in your project name or in the directory path to your project. Spaces will cause an "Internal Error" when you try to simulate your design.

Select “Schematic/Verilog HDL” for your project type.

Confirm that you have no spaces in your project name or project folder

Look at the top blue strip of the Project Navigator window to see the full name and location of your project. There must not be any spaces anywhere in the path or filename.

Specify the device type

Double click the yellow and black device icon in the left panel.

Select “GAL Device” for Family.

Select “GAL22V10B” for Device.

Select “24DIP” for Package.

Select “-15” for speed grade.

Click “OK”, and say “Yes” to prompt about changing device kits, and say “Yes” to prompt about losing previous constraints.

Create a new Verilog file for the circuit description

Select “Source | New”.

Select “Verilog Module”

Enter a single word for Module Name. Begin with a letter, and use only legal Verilog characters (letters, numbers, underscore).

Enter a single word for File Name. This is the name of the file that will store your Verilog code.

 Do not use spaces in your file name.

Click “OK”.

Enter your Verilog circuit description.

Enter text as needed.

Save your file (use Ctrl-S or push the save-to-disk icon).

Example Verilog circuit description:

module Demo (a,b,c);

input a;  //exemplar attribute a loc P2
output b; //exemplar attribute b loc P14
output [2:0] c;  //exemplar attribute c loc P20P21P22

assign b = ~a;
assign c = {a,a,a};

endmodule

 

NOTE 1: The "exemplar" comments above are a special type of Verilog comment. A standard Verilog compiler will ignore these, but the LeonardoSpectrum synthesis tool in ispLEVER will pick up the pin location instructions and use them for your design. You must follow the format exactly as shown (no space between "//" and "exemplar", and "P" before the pin number). The output declaration for port c above shows how to make multiple pin assignments for a bus.

NOTE 2: Ensure that you have selected "LeonardoSpectrum" under "Options | Select RTL Synthesis" in the Project Navigator window.

Enter your circuit test input stimulus (“test vectors”)

Select “Source | New”, select "ABEL Test Vectors", then select a name for your test vectors file.

Select your .v file in the left "Sources" panel, then double-click the "ABEL Test Vector Template" process in the right "Processes" panel.

Copy the template text that was generated in the bottom scrolling window into the test vector file.

Find the TEST_VECTORS section of the template and add your test vectors.

Example (to match Verilog file above):

0 -> .X. ;
1 -> .X. ;
0 -> .X. ;
 

Save your file (use Ctrl-S or push the save-to-disk icon).
 

Verify Your Design Using Simulation:

Prepare your design for simulation

Select the Project Navigator window.

Single click the test vectors (.abv) line in the left panel.

Double click “Functional Simulation” in the right panel.

If you have syntax errors, edit your Verilog file, save it, and click “Functional Simulation” again. Repeat until all syntax errors have been removed.

Simulate your design

Push the “Run” button (exclamation point icon) in the automatically opened Simulator Control Panel window. Your design will be simulated and the results displayed in the Waveform Viewer window.

Iterate until your design is correct.

Return to your Verilog file. Make edits as needed, then save your file.

Double click “Functional Simulation” to cause the system to re-read your file and prepare a new simulation.

Press the “Run” button in the Simulator Control Panel. Your updated waveforms should appear.

If you add new signals and do not see them in the Waveform Viewer, select “Edit | Show...” in the Waveform Viewer and select the desired signal(s) to be added to the display.

 Do not proceed until your design simulates correctly according to your design intent!

Implement Your Design to Produce a JEDEC File:

Create a JEDEC file

Return to Project Navigator window.

Single click the yellow and black device icon in the left panel.

Double click “JEDEC File” in the right-hand side panel.

Confirm that your inputs and outputs were connected to the correct pins

Double click “Chip Report”.

Review the pinout diagram to confirm that it is correct.

Always confirm that the input and output pins have been placed correctly before placing the GAL in your circuit.

NOTE: Do not be concerned if you see some of your outputs indicated as complemented (for example, your output signal is called "Dout" and it appears in the chip report as "!Dout"). This is merely an indication of the specific method used to create the Boolean expression for that output. The chip output levels will behave exactly as they did in simulation.

Locate your JEDEC file

 Open Windows Explorer window (hold down Windows key and press E).

Navigate to your project folder. Note that the path to your project is contained in the title bar of the Project Manager window. Alternatively, do “File | Full Project Path”.

Locate the .JED file.

Program GAL with JEDEC File:

Insert GAL in device programmer

Always carry your GAL chip in a piece of conductive foam to avoid causing damage from electrostatic discharge (ESD).

 Notched end of chip is oriented upwards (see the drawing on the left side of the programmer). If device does not have a notch, then ensure that pin 1 (marked by a dot) is at the upper left.

 Non-notched end of chip is placed flush at bottom of the socket.

Close the lever at the lower right corner of the socket to properly connect the chip to the socket.

Start Xeltek programmer application

In Windows, do Start | Programs | SUPERPRO 280.

Select GAL device

Select “Device | Select”.

Choose “PLD” option on the right side of the panel.

Select “Lattice” for Manufacturer.

Select “GAL22V10” for Device Name.

Load JEDEC file

Select “File | Load”.

Navigate to your .JED file and select it.

Program the GAL

Select “Device | Run”

Select “Program” for Function.

Click “Run” button to program the GAL

Test Your Design:

Apply external stimulus from your own circuitry.

The GAL is a 5-volt device.

Ensure that any clock waveforms you apply to the circuit are zero to five volts.