Transforming Your Concept into an FPGA Bitfile: Step-by-Step Instructions

Summary

This document describes the step-by-step process to create, simulate, and implement a Xilinx FPGA-based design.

Required Software

Required Hardware

Step 1 of 7 - Create your conceptual design

1. Draw the I/O block diagram of your circuit, i.e., draw a rectangle with pins sticking out, and write a name for each signal pin.
    

2. If you are targeting the XS40 board for stand-alone FPGA operation, add a pin to hold the microcontroller in reset mode and another pin to hold the RAM output in inactive mode.
   
   Note: The XS40 includes a variety of peripheral devices that are permanently connected to the FPGA. Holding the 8031 microcontroller reset pin in the high state will deactivate the micro and force all of its pins to the high-impedance state, effectively removing the micro from the board. Likewise, holding the RAM output enable high will force the output pins to high-impedance, thereby avoiding any conflicting signals.
    

3. Draw the high-level (register-level) diagram of your design. This diagram will help you visualize the hardware when you write your circuit descriptions.

Step 2 of 7 - Create the template files

1. Start Verilog Template Maker (VTM).
    

2. Enter the number of input and output ports; bit vectors (busses) count as a single port. Next, enter the information specific to your design (module name, port names, port widths, and descriptive comments).
    

3. Select "Make Circuit" to create the synthesizable circuit template. Copy the text into a file called "circuitname.v", replacing "circuitname" with a descriptive label for your design.
    

4. Select "Make Testbench" to create the testbench template. Copy the text into a file called "circuitname_TB.v".
    

5. Select "Make UCF" to begin the process of creating your user constraints file. Select the XS-40 resources that you require for your design, then match your specific port names to the specific XS-40 resources. Copy the resulting text into a file called "circuitname.ucf".

Step 3 of 7 - Enter your Verilog descriptions

1. Insert your circuit functionality into "circuitname.v". Add additional comments (documentation) into the file as needed.
   
   NOTE 1: VTM assumes all outputs will be 'reg' identifiers. If you need to use continuous assignment ('assign' statement), then simply delete or comment out the associated 'reg' declaration.
   
   NOTE 2: You may wish to use the Silos text editor. Select "File | New", copy/paste the text from VTM, then save to a .v file (you need to specify the .v file suffix yourself). You may find it necessary to do an intermediate copy/paste into Windows Notepad editor in order for Silos to properly recognize the end-of-line characters. Also, the Silos text editor includes an option to color code the text file according to Verilog syntax: select "Options | Syntax Color Coding" option.
    

2. Insert your testbench simulation into "circuitname_TB.v".

Step 4 of 7 - Perform functional verification using simulation

1. Create a new project in Silos by selecting "Project | New", then enter a name for your project. I recommend that you create a new folder for your project.
    

2. Add your Verilog files to the project by navigating to the location of your .v files, and double clicking each file to add it to the project. Click "OK" when finished.
    

3. Run the simulator by pressing the green "GO" button. If all goes well, you will see some commentary followed by the "Ready:" prompt. If errors are reported, then open the offending .v file and correct the problem. Press Alt+F5 key combination to reload the .v files and rerun the simulation.
    

4. View the simulation results as a timing diagram by clicking the the "Open Explorer" and "Open Analyzer" buttons in the top icon row of Silos. In the Data Explorer window, single click the module name (it should be the same name as your testbench module). Click and drag the signal names from the Data Explorer window to the Data Analyzer window.
   
   Once the timing diagram is visible (and the Data Analyzer window is selected), use the toolbar helpers as needed, e.g., zoom in, zoom out, and zoom fullscreen.
   
   You can change the display bus values from hexadecimal to decimal or binary by right-clicking on a signal name and choosing "Set Radix."
    

5. Iterate between editing your files and re-simulating until you achieve correct results for your circuit functionality. You can edit the .v files directly in Silos (use "File | Open"). After updating your file, press Ctrl-S to save the file, then press Alt+F5 to reload and resimulate. The simulation results will show up immediately in the waveform window.
   
   NOTE: You will find it convenient to use "Window | Tile" mode to display all your windows simultaneously.

Step 5 of 7 - Implement your design as a bitstream file

1. Start Xilinx ISE, and create a new project by selecting "File | New Project..." (note that Xilinx will open the most recently-used project, so you want to begin from scratch here).
    

2. Select a single word for the name of your project, and select the directory for your project files.
    

3. Enter the following information (touch the right side of the white field to enable the pull-down menu):

4. Add your synthesizable circuit "circuitname.v" to the project by selecting "Project | Add Source..." in the Project Navigator window. Navigate to the folder that contains "circuitname.v". Do not add the testbench file.
   
   NOTE: It is possible to write a Verilog description that simulates successfully in Silos, and yet is incompatible in some way with the hardware synthesis or implementation steps in Xilinx ISE. This is not necessarily a shortcoming of ISE, but rather is due to the fact that Verilog is inherently a simulation and modeling language, and hardware synthesis tools only deal with a subset of the language. The bottom line: you need to learn how to write synthesizable descriptions.
    

5. Add your UCF file to the project as follows: Expand the "Design Entry Utilities" process in the lower left "Processes" panel by clicking the "+" symbol. Then, expand the "User Constraints" process. Double-click "Edit Implementation Constraints File." Delete all of the template text (do Ctrl-A followed by delete key) and paste in your own UCF file contents generated by Verilog Template Maker. Select "File | Save" on the Notepad window, then close the Notepad window.
    

6. Start the hardware synthesizer by first selecting your top-level module in the upper left "Sources" panel, then double-click the "Synthesis" process on the lower left "Processes" panel.
   
   NOTE: A green checkmark on a process means all is well; a yellow exclamation point means one or more warnings were generated, and a red X means a fatal error. You can find the error messages in the bottom scrolling window at the bottom of the Project Navigator, and in some cases you can also find the error messages in the report file associated with each process in the lower left "Processes" window (you need to expand the hiearchy to find the reports).
    

7. Start the implementation tools by double-clicking the "Implement Design" process on the lower left "Processes" panel.
    

8. Create the bitstream file by double-clicking the "Generate Programming File" process on the lower left "Processes" panel.
   
   NOTE: In general you can run all previous processes by double-clicking the desired process. For example, if you make a change to the .v file, the implementation data will be cleared (all the checkmarks vanish), and double-clicking the "Generate Programming File" process will cause the synthesis and implementation processes to run automatically.
    

9. Verify that your pinout is correct by expanding the "Generate Programming File" process and double-clicking the "Programming File Generation Report."

Step 6 of 7 - Download bitstream file to XS40 board

1. Ensure that the XS40 board is powered and connected by parallel cable to the computer's parallel port.
    

2. Open a Windows Explorer window (Windows button + E) and navigate to the same folder as is displayed in the top blue stripe of the Xilinx Project Navigator window.
    

3. Locate the bitstream file "circuitname.bit" (click "Type" to sort by type, and look for the .BIT file).
    

4. Start the XS40 download application called GXSLOAD. Ensure that you have the correct board selected - "XS40-010XL".
    

5. Drag the .BIT file from the Windows Explorer window to the GXSLOAD application's "FPGA/CPLD" panel on the left and click "Load".
   
   NOTE: GXSLOAD operates "open loop," meaning that it does not receive any communication back from the XS40 board. Thus, GXSLOAD may report that all is well, even when the XS40 board is not powered or connected to the computer.
   
   TIP: Make or obtain a simple test bitstream file that you can use as a "sanity test," i.e., lighting the LED segments in a specific pattern.
    

Step 7 of 7 - Test your design

1. Apply stimulus from the computer using the GXSPORT application. The eight signals are connected directly to the FPGA.
   
   NOTE: You need to use a special Verilog technique in order to make your design responsive to the upper two bits from the parallel port. Ask your instructor to learn how to make this work.
    

2. You can apply stimulus from your own external circuitry. Remember that the FPGA on the XS40 board operates at 3.3 volts, so output signals never exceed this value. The inputs are 5-volt tolerant. See the document Location of Vdd and Ground Pins to ensure that your circuitry shares a common ground with the FPGA.
    

3. Change the XS40 clock frequency as needed using the GXSSETCLK application. Follow the instructions carefully, since you will need to adjust a jumper setting as part of the process. See the document About the Programmable Oscillator for details about available clock frequency settings.

Additional Tips

1. You can edit your Verilog files in the Xilinx ISE environment. Double-click the .v file in the "Sources" panel to open it in the editor.
    

2. If you need to change the target device once you have implemented the project (e.g., take your design from an XC4000 family device to a Spartan device), right-click on the target device line in the "Sources" panel, select "Properties", enter your new information, and then re-implement your design by double-clicking the "Implement" process.
    

3. You can remove files from your project by selecting the desired file from the "Sources" panel, right-clicking, and choosing "Remove". Note that your file does not get deleted from the filesystem, but simply becomes unknown to the Xilinx Project Navigator.
    

4. If something seems "not quite right" about the behavior of the system, try selecting "Project | Delete Implementation Data" to start from the beginning.
    

5. You can learn the resource usage of your design such as CLB count (configurable logic blocks) by opening the "Map Report" located in the "Processes" hierarchy under "Implement Design | Map | Map Report".
    

6. You can see a schematic representation of your system by looking in the "Processes" hierarchy under "Synthesize | Create Functional Structure | View Schematic (Func.)".
    

7. You can see how your design was routed on the chip itself by looking in the "Processes" hierarchy under "Implement Design | Place & Route | View/Edit Routed Design". Just look, don't actually change the design!