Verilog Examples

Verilog Examples

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Testbenches

Description	Synthesizable Circuit	Testbench
Simple demonstration of testbench technique	demo.v	demo_TB.v
Use a "for" loop to efficiently test all possible input combinations of a combinational circuit	combi_ckt.v	combi_ckt_TB.v
Include text comments in your waveform output to facilitate interpretation		comments.v
Use a "task" to automate the production of waveforms		taskdemo.v

Finite State Machines

Description	Synthesizable Circuit	Testbench
FSM using separate 'always' blocks for next-state decoder, output decoder, and state register	fsm_example.v	fsm_example_TB.v

Sequential Circuits

Description	Synthesizable Circuit	Testbench
Counter with variable step size, and controls for count direction, count enable, and initial value	seq4.v	seq4_TB.v

Compiler Directives

Description	Synthesizable Circuit	Testbench
Use an "`ifdef" compiler directive to set a parameter to one value for simulation and another value for synthesis. Particularly useful for clock divider circuits that require a small value for simulation and a large value for synthesis.	ifdef.v

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ECE333: Digital Systems (W 2002-03)
Department of Electrical and Computer Engineering
Rose-Hulman Institute of Technology

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Last updated: 03/10/05.