"Half-Gate" FPGA Design and Character Generator

Introduction

This laboratory will give you confidence to use the CAD tools associated with targeting a Verilog description to a Xilinx FPGA. To begin with, you will practice with the CAD tools themselves by implementing "half of a NAND gate" (an inverter). Next, you will implement a combinational circuit to display characters on a seven-segment display.

Objectives

Parts List

No additional parts required for this lab.

Equipment

Software

Prelab

1. Check out one XS-40 FPGA evaluation board from the Instrument Room (only one per lab group). Your kit should contain the XS-40 board itself, a breadboard, a 9-volt plug-in power supply, and a parallel port cable.
    
2. If you wish to create a complete local installation of all software packages that you will need during the upcoming weeks, then install the following:
   
   -- Xilinx ISE Student Edition 4.2i (this was packaged with your textbook).
   -- SimuCad Silos 2001 Verilog behavioral simulator
   -- Xess Corp. XSTOOLS for XS-40 FPGA board
    
3. Review (skim) the XS-40 User's Manual to learn about the resources available on the FPGA board. In particular, study the "Simplified Schematic" page (second bookmark from the end).
    
4. Study carefully the Concept to FPGA: Step-by-Step Instructions document. This is your roadmap for the design, verification, and implementation process. You may also wish to refer to PLD Advisor for worked examples.
    
5. Create a Verilog description for half of a NAND gate (the so-called "half-gate" circuit, or inverter).
   
   You must use the two-file Verilog technique, i.e., make one .v file for the synthesizable circuit, and another .v file for the testbench. Include hardcopy of both files.
   
   Verify your design in Silos, and include hardcopy of the waveforms from your simulation.
    
6. Create a Verilog description for a character generator for the seven-segment display. The character generator is a combinational circuit that accepts a four-bit binary value and generates a unique character to be displayed on the seven-segment LED (the LED segments are active high). Feel free to be creative; you are not restricted to only alpha-numeric characters.
   
   Again, you must use the two-file Verilog technique. Include hardcopy of both files.
   
   Verify your design in Silos. Include written annotations on your waveform to explain your simulation results.
    
7. A photocopy of your prelab pages is due at the beginning of the class the day before lab.

Lab

Please use the Lab Help Queue to request assistance in lab.

NOTE: If you need a "sanity test" of your XS40 board, download xs40demo.bit to your board, set XSPORT Bit 0 to zero, and you should see a single moving segment traveling clockwise around the periphery of the LED display. If you would like to create the bit file yourself, the Verilog source file is xs40demo.v and the UCF file is xs40demo.ucf.

1. Carry out the complete implementation process for your half-gate design. Use XSPORT Bit 0 as the input to your inverter. Use one of the LED segments as the output.
    
2. Demonstrate your half-gate circuit to the instructor. You may not proceed until you complete this step!
    
3. Carry out the complete implementation process for your character generator. Use XSPORT Bits 3 to 0 as the four-bit input. Use the LED segments as the output.
    
4. Demonstrate your character generator circuit to the instructor.
    

All done!