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Problem 1Wakerly 3.16 Problem 2(a) Analyze the circuit below to determine the outputs F and G as a function of inputs A and B. Use a function table to help you keep track of transistor on/off states. (b) Draw the circuit symbol of this gate. Problem 3A particular logic family has the following specifications:
VILmax = 35% of VCC VIHmin = 80% of Vcc VOHmin = VCC – 5% of VCC
(a) What is the LOW-state DC noise margin? Problem 4Given the voltage input waveform shown below: Assume a 5V system power supply. (a) Plot the response to the waveform of a standard inverter assuming a 3.0V threshold voltage. (b) Plot the response to the waveform of a Schmitt-trigger inverter that has a low-to-high threshold of 3.0V and a high-to-low threshold of 2.0V. Problem 5Suppose you wish to treat each of the four systems below as a "lumped-parameter" system. Determine the minimum permissible pulse rise time that will make your assumption valid. (a) 7 inches of coaxial cable Problem 6Note: Use the Java applet at http://www.ecse.rpi.edu/Courses/F97/35210/java/Transline/tr_lines.htm or http://hibp.ecse.rpi.edu/~crowley/java/Transline/tr_lines.htm for this problem. Evaluate the following transmission line termination techniques -- comment on
how quickly the signal settles down, whether or not you would get multiple
transitions if a CMOS gate were to be connected to the end of the t-line, and
whether or not the CMOS gate receives a solid HIGH level input voltage after the
transient has died out. Use the Java applet to display the voltage at the end of
the t-line (set X=100), and use Zo = 100 ohms. Include a sketch of each
waveform. (c) Source resistance = 20 ohms, load resistance = 100 ohms. (d) Source resistance = 100 ohms, load resistance = open circuit (e) Source resistance = 100 ohms, load resistance = 100 ohms. |
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