General Instructions

For each problem:

1. Draw the symbol for the device showing inputs and outputs,

2. Develop a synthesizable Verilog description,

3. Develop a testbench, and

4. Verify by behavioral simulation that your circuit meets specification.

Include hardcopy of all Verilog code.

Include annotated hardcopy of simulation results (“annotated” means that you include handwritten comments on the waveforms to explain the input stimulus, and to clearly explain how the simulated output shows that your circuit is working properly).

Problem 1

Up-Down Counter – Positive edge-triggered, asynchronous reset (active high), 16 bits wide. A control input determines whether counter counts up or down. When counting up, count increments by 3. When counting down, decrements by 2.

Problem 2

Loadable Down Counter with Variable Increment – Negative edge-triggered, asynchronous reset (active high), 4 bits wide. Includes two control inputs, LOAD and ENABLE. When LOAD is asserted, counter is loaded with 4-bit input value DATAIN on the next clock trigger. When ENABLE is asserted, the counter decrements. When count value is zero, the output EQZERO is asserted. The counter decrements by the value on the 4-bit input bus DECVAL.

Problem 3

Shift Register – Positive edge-triggered, asynchronous reset (active low), 10 bits wide. Left shifts data contained in the register. Shifts value on SERIALIN into the right side of the register.

Problem 4

Programmable Clock Divider – Accepts an input clock signal at frequency f and produces an output clock signal at frequency f/N, where N is three-bit input value in the range 2₁₀ to 7₁₀. The duty cycle of the output clock should be as close to 50% as possible. Verify your design for at least two different values of N.