General Instructions

For each problem:

1. Draw the symbol for the device showing inputs and outputs,

2. Develop a synthesizable Verilog description,

3. Develop a testbench, and

4. Verify by behavioral simulation that your circuit meets specification.

Include hardcopy of all Verilog code.

Include annotated hardcopy of simulation results (“annotated” means that you include handwritten comments on the waveforms to explain the input stimulus, and to clearly explain how the simulated output shows that your circuit is working properly).

Problem 1

Decoder – 2-to-4 decoder (also called 1-of-4 decoder). Active low outputs. Only one output is enabled at a time. An additional input control signal (active high) is used to enable the decoder output; all outputs remain high if the enable is deasserted.

Problem 2

Adder / Subtractor – Accepts two 16-bit inputs A and B. Produces a 17-bit output Y. A control line input determines whether the operation is “A plus B” or “A minus B”.

Problem 3

Bit Rotater – Accepts an 8-bit value and produces an 8-bit output. Three control lines (3-bit bus) determine how many bit positions to right-rotate the input data. For example, a control code of 000 causes the input pattern b₇b₆b₅b₄b₃b₂b₁b₀ to appear on the output unchanged. A control code of 001 causes the output b₀b₇b₆b₅b₄b₃b₂b₁, value 010 causes the output b₁b₀b₇b₆b₅b₄b₃b₂, and so on.

Problem 4

Range Tester - Accepts a 12-bit value interpreted as an unsigned binary number M. Generates three active-high outputs to indicate when the input is in a specific range: 0 <= M <= 100, 100 < M <= 1000, and M > 3000  (all numerical values for the ranges are base 10).