module

Controller

// System controller.

(
// Clock and reset:
iG$MasterClock,		// Master clock
iG$MasterReset,		// Master reset (active high)

// Condition signals from datapath:
iS$KeyIsPressed,	// Asserted when any key is pressed
iS$IntervalIsComplete,	// Indicates end of time interval
iS$SumIsCorrect,	// Indicates when sum is valid
iS$KeyPressingIsFinished,	// Indicates when correct number of keys
								// have been pressed

// Control point signals to datapath:
oC$InitializeTimer,	// Set timer to beginning of interval
oC$EnableTimer,			// Allow timer to operate
oC$AddKey,			// Add key value to sum
oC$ClearSum,			// Clear the sum

// Primary outputs:
oE$ActivatePassLED,	// "PASS" LED 
oE$ActivateFailLED,	// "FAIL" LED 
oE$ActivateSolenoid	// Solenoid control

);

// Declare port modes
input iG$MasterClock;
input iG$MasterReset;
input iS$KeyIsPressed;
input iS$IntervalIsComplete;
input iS$SumIsCorrect;
input iS$KeyPressingIsFinished;
output oC$InitializeTimer;
output oC$EnableTimer;
output oC$AddKey;
output oC$ClearSum;
output oE$ActivatePassLED; 
output oE$ActivateFailLED; 
output oE$ActivateSolenoid;

// Declare registered identifiers
reg [6:0] r$State,r$NextState;
reg oC$InitializeTimer;
reg oC$EnableTimer;
reg oC$AddKey;
reg oC$ClearSum;
reg oE$ActivatePassLED; 
reg oE$ActivateFailLED; 
reg oE$ActivateSolenoid;

// Assign states
parameter pQ$Initialize		= 7'b0000001;
parameter pQ$WaitForKeyPress	= 7'b0000010;
parameter pQ$AddToKeysum			= 7'b0000100;
parameter pQ$WaitForKeyRelease	= 7'b0001000;
parameter pQ$SequenceFailed		= 7'b0010000;
parameter pQ$SequencePassed		= 7'b0100000;
parameter pQ$ErrorTrap			= 7'b1000000;


// State register
always @ (posedge iG$MasterClock or posedge iG$MasterReset)
	if (iG$MasterReset) 
		r$State <= pQ$Initialize;
	else
		r$State <= r$NextState;
		
// Next-state decoder
always @ (r$State or iS$KeyIsPressed or iS$IntervalIsComplete or iS$SumIsCorrect
				or iS$KeyPressingIsFinished)
	case (r$State)
		pQ$Initialize :
			r$NextState <= pQ$WaitForKeyPress;
		pQ$WaitForKeyPress : 
			r$NextState <= (!iS$KeyIsPressed) ? pQ$WaitForKeyPress : pQ$AddToKeysum;
		pQ$AddToKeysum :
			r$NextState <= pQ$WaitForKeyRelease;
		pQ$WaitForKeyRelease :
			if (iS$KeyIsPressed)
				r$NextState <= pQ$WaitForKeyRelease;
			else
				if (!iS$KeyPressingIsFinished)
					r$NextState <= pQ$WaitForKeyPress;
				else
					if (iS$SumIsCorrect)
						r$NextState <= pQ$SequencePassed;
					else
						r$NextState <= pQ$SequenceFailed;
		pQ$SequenceFailed : 
			r$NextState <= (!iS$IntervalIsComplete) ? pQ$SequenceFailed : pQ$Initialize;
		pQ$SequencePassed : 
			r$NextState <= (!iS$IntervalIsComplete) ? pQ$SequencePassed : pQ$Initialize;

		default : r$NextState <= pQ$ErrorTrap;
	endcase		

// Output decoder
always @ (r$State) begin
	// Default output values
	oC$InitializeTimer <= 0;
	oC$EnableTimer <= 0;
	oC$AddKey <= 0;
	oC$ClearSum <= 0;
	oE$ActivatePassLED <= 0; 
	oE$ActivateFailLED <= 0; 
	oE$ActivateSolenoid <= 0;

	case (r$State)
		pQ$Initialize :
			begin
				oC$InitializeTimer <= 1;
				oC$ClearSum <= 1;
			end
		pQ$WaitForKeyPress : 
			begin
			end
		pQ$AddToKeysum :
			begin
				oC$AddKey <= 1;
			end
		pQ$WaitForKeyRelease :
			begin
			end
		pQ$SequenceFailed : 
			begin
				oC$EnableTimer <= 1;
				oE$ActivateFailLED <= 1; 
			end
		pQ$SequencePassed : 
			begin
				oC$EnableTimer <= 1;
				oE$ActivatePassLED <= 1; 
				oE$ActivateSolenoid <= 1;
			end
		pQ$ErrorTrap :
			begin
				oE$ActivateFailLED <= 1; 
			end
	endcase		
end

endmodule