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ece533 | doering | ece labs | ece | rhit |
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Learn how to design a hybrid microcontroller/FPGA system |
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Design a system using memory-mapped I/O interfacing |
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Learn how to compile a C program for 8031 microcontroller |
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Experience design re-use |
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Keil C51 C compiler for 8031 microcontroller |
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Silos 2001 Verilog behavioral simulator |
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Xilinx ISE 4.2i FPGA implementation tools |
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XSTOOLS (GXSPORT, GXSLOAD, GXSSETCLK) |
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AT-style keyboard with PS/2 interface connector |
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XStend board and XS-40 board combination |
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Parallel port cable |
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9V 500mA DC power supply |
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Winbond W78C32B datasheet (very close to the W78C31B on the XS40 board; I have not been able to find the datasheet for the W78C31BP-24 device on the XS40, so perhaps it is obsolete) |
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Keil's "Device Database" entry for Winbond W78C32B; includes software examples. |
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C51 compiler documentation: look in "C:\Keil\C51\HLP" installation folder on your computer and find the "C51.pdf" file. |
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Keil tech support pages: Writing to an output port and reading from an input port (the latter is not needed for this project, but it's nice to know how) |
Study the Verilog file
8031template.v (the corresponding UCF file is
8031.ucf; the testbench
8031template_TB.v is available, too, should you need it). This file contains an interface "shell" for your FPGA system as
well as numerous examples of readable and writeable registers. The Verilog file
contains documentation that is designed to be read, and contains a variety of
useful information you need to know.
Study the C file
8031template.c. This file shows an example of an 8031 program that can
interact with the memory-mapped registers in the
8031template.v system. In particular,
note the use of "XBYTE" to refer to specific memory addresses.
Study the Keil C
compiler instructions.
In order to ensure that you understand the hardware described in 8031template.v, draw the register-level diagrams of the following (be sure to include bus widths on your diagram):
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Interconnections between the board-level components: 8031, FPGA, RAM, oscillator, and LED display |
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Hardware described in "Basic 8031-SRAM-FPGA Interface" section |
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Hardware described in "Examples: 8031-Writable Registers" |
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Hardware described in "Examples: 8031-Readable Registers" |
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Hardware described in "Example: 8031-Controllable Process in
FPGA" |
Implement 8031template.v
to a .bit file, and compile 8031template.c
to a .hex file. Use GXSLOAD to download both the .hex file and the .bit
file to the XStend board (drag the .hex file to the center panel called "RAM").
Use GXSPORT Bit 0 to operate the active-low master reset).
The system to be designed is illustrated below:
[ insert diagram ]
The system will operate as follows:
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Look for scan codes for keypad 0 to 7 |
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Activate the corresponding Port 1 bit when the key is pressed, and deactivate the bit when the key is released. For example, pressing keypad 2 will cause Bit 2 of Port 1 to go to a high level, and releasing the key will cause the bit to go low again. |
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Use the XS40 LED to display the number of keys that are currently pressed. |
The FPGA will implement the PS/2 interface, memory-mapped registers, and font generator for the LED display. The remaining processing tasks will take place on the 8031.
NOTES:
Do not press the SPARE button at any time (it interferes with Port 1 Bit 7)
Ensure that all DIP switches remain in the OFF position (these interfere with the remaining Port 1 bits)
Observe the Port 1 activity using eight digital inputs on the mixed-signal oscilloscope
Use the C preprocessor directive "#include <reg51.h>" (omit the quotation marks) to declare names for the "special function registers" (sfr data type). You can then set all eight Port 1 bits using a statement such as "P1 = 0x45;" (this statement will cause Port 1 bits 7 down to 0 to become 01000101).
The C program should use a polling technique to continually check the PS/2 status register in your FPGA design.
The PS/2 status register should automatically clear itself when the PS/2 data register is read. This will ensure that the micro does not accidentally re-read the same PS/2 data register value.
Hardcopy of all Verilog code produced
Hardcopy of all 8031 C code produced
Memo detailing your design process and results. Describe the algorithms you implemented on the 8031, and also describe the technique you used for your PS/2 status and data register behavior.
Demonstration of your design to instructor (obtain initials)
Beginning of lab two week's from today
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