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Simulating and Implementing Designs with Instantiated Cores
Summary
This document describes the step-by-step process to create,
simulate, and instantiate a Xilinx "LogiCORE" core in your design. The overall
process is:
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Create your own HDL design
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Create a core from Xilinx Core Generator
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Instantiate a behavioral model of the core into your HDL
design, and perform functional verification using a behavioral simulator
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Instantiate a synthesizable version of the core into your HDL
design, and synthesize and implement your overall design to a bitstream file
Required Software
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Xilinx ISE 4.2i FPGA implementation software |
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Simucad Silos 2001 Verilog behavioral simulator |
Overview of Detailed Example
A running example will be used to step through the design
process. A system containing your own HDL description will be merged with a core
to produce a single design.
The system be be designed is diagrammed below; the "core" will
be the 2's complementer device from the Xilinx CORE Generator Library):
[insert picture here]
The circuit is not intended to do anything particularly useful,
but rather will demonstrate the combination of a Verilog description for
inferred hardware (the 7-segment display drivers) and an instantiated core from
the Xilinx CORE Generator tool.
Use boldfaced values in square brackets to follow along
with the running example.
Step 1 of 7 - Create a new Xilinx project
After starting Xilinx, do "File | New Project..." and enter your
project information. Remember to select the following options:
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Device Family = XC400XL |
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Device = xc4010xl-3pc84 |
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Design Flow = FPGA Express Verilog |
Step 2 of 7 - Start the Core Generator tool
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Select "Project | New Source"
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Select "Coregen IP"
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Enter a single word for filename [ comp4 ]
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Accept the default for location
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Ensure that "Add to Project" checkbox is checked
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Click "Next" and "Finish"
Step 3 of 7 - Select, configure, and build the core
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Expand (by double-clicking) the hierarchical list on the
left-side panel until you find the desired core [ look for "Math Function",
then "Complementers" ]
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Double-click the desired core in the right-side panel [
select "1s or 2s Complementer" ]
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Select "Data Sheet" button to review the operational and I/O
details of the core. The data sheet also lists the CLB (configurable logic
blocks) resource requirements as a function of your parameter choices.
Remember that the XC4010 has a total of 400 CLBs available.
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Enter a single word for the "Component Name" [ comp4 ]
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Select the specific core parameters necessary for your design
[ "Port Width" = 4, "Twos Complementer" selected ]
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Optional: select the "Display Core Footprint" if you wish to
see a summary of the core's implementation details (including size) after the
core has been generated.
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Select "Generate" to build the core
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Click "Dismiss" when finished
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Close the Core Generator tool when finished
Note that your core has been added to the project (look at the
upper left-side panel). You can update the core by single-clicking the core
entry in the source list, expanding the processes list in the lower left-side
panel, double-clicking "Manage Cores", and selecting your core from the list at
the bottom of the Core Generator panel. Alternatively, you can right-click the
core entry in the source list (upper left-side panel) and select "Open".
Step 4 of 7 - Simulate the core
I recommend that you simulate the core in isolation in order to
learn how it works. In order to do this, you need to create a testbench for the
core, and you need to tell Silos where all the files pertinent to behavioral
simulation are located. Note that Core Generator produces two distinct
outputs: (1) the netlist information for implementation, and (2) behavioral
models for simulation. Make no attempt to add the behavioral model to
your project for hardware synthesis.
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In Xilinx Project Navigator, open the core's Verilog "wrapper
file" [ comp4.v ] by selecting "File | Open..." or by clicking the
"file open" icon at the upper left. This file contains the module name and
port names for your core. Make note of the module name [ comp4 ] , the
port names [ a, inv, c, ce, and q ] , and the port widths [ 4, 1, 1,
1, and 4, respectively ].
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Use
Verilog Template Maker (http://www.rose-hulman.edu/~doering/php/vtm.php)
to create a testbench .v file [ comp4_TB.v ]. You do not need to make a
synthesizable circuit or UCF file. Be sure that you correctly enter the
following information for your core:
- number of input ports [ 4 ]
- number of output ports [ 1 ]
- number of bidirectionals [ 0 ]
- module name [ comp4 ]
- "use standard prefixes" turned off
- port names and widths for inputs [ a, 4; inv, 1; c, 1; ce, 1 ]
- port names and widths for outputs [ q, 4 ]
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Start a new Silos project, and add your testbench [
comp4_TB.v ] to the files list.
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Add the wrapper file [ comp4.v in Xilinx project folder ]
to the files list. In Silos, you need to navigate to the Xilinx project
folder and add the .v file that has the same name as your core.
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In Xilinx Project Navigator, look at the wrapper file [
comp4.v ] and note the name that follows just after the comment "synopsys
translate_off" [ CMPSVHT ]. This is the Verilog behavioral model
itself. Add this file to the Silos files list: within Silos, navigate to
"C:\Xilinx\verilog\src\XilinxCoreLib" and select the Verilog file with the
same name you found in the wrapper file [ CMPTSVHT.v ].
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Insert the test sequence in your testbench file [
comp4_TB.v ]. The exact details vary from core to core, but in general you
are trying to make sure that you understand how the core works. Most (maybe
all) of the Xilinx cores have "registered outputs," meaning that you need to
apply one or more clock cycles to see a valid output emerge.
[ Insert the following test sequence in comp4_TB.v ]:
initial begin
// Initial values for input stimulus:
a = 4'h5;
inv = 1'b0;
c = 1'b0;
ce = 1'b0; // Enable the core
#40 ce = 1'b1; // Enable inversion
#40 inv = 1'b1; // Change the input value
#40 a = 4'hc; // Disable inversion
#40 inv = 1'b0; // All done!
#40 $finish;
end always #5 c = ~c;
Simulate the core and revise your testbench until you feel
confident that you understand how the core works.
Step 5 of 7 - Enter HDL description
Once you have a good understanding of the generated core (or
cores) in your design, you can proceed to build the complete system.
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Use
Verilog Template Maker to create the synthesizable circuit, testbench, and
UCF file for your complete system. Be sure that you correctly enter the
following information for the complete system:
- number of input ports [ 4 ]
- number of output ports [ 6 ]
- number of bidirectionals [ 0 ]
- module name [ TopLevel ]
- "use standard prefixes" turned on
- port names and widths for inputs [ Clock, 1; Invert, 1; Enable, 1;
DataIn, 4 ]
- port names and widths for outputs [ InvertLED, 1; EnableLED, 1;
LeftSevenSeg, 7; RightSevenSeg, 7; MicroReset, 1; RAMOE, 1 ]
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In Xilinx Project Navigator, open the core's Verilog
"instantiation template" [ comp4.veo ] by selecting "File | Open..." or
by clicking the "file open" icon at the upper left. This file contains the
template for instantiating the core into your own design..
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Insert the functionality for the synthesizable circuit and its
testbench. See toplevel.v,
toplevel_TB.v,
sevenseg.v, and
toplevel.ucf for
complete files. [insert links]
Step 6 of 7 - Simulate entire system
NOTE: Some cores may be too large to simulate in the demo
version of Silos. Alternatively, you may be able to simulate the core by itself,
and then find that the combined system is too large for the demo version. Your
best bet in this case is to do a good job simulating the pieces, and then the
integrated version should have a good chance of working properly.
Step 7 of 7 - Implement entire system
Return to Xilinx Project Navigator, and add all Verilog files
associated with your complete design [ toplevel.v, sevenseg.v ]. Don't
forget to specify your UCF file [ toplevel.ucf ]. Do not add
testbench files or Xilinx behavioral Verilog files.
Highlight the top level module in the upper left-side sources
panel, then double-click the "Generate Programming File" process in the lower
left-side panel.
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