HierarchyFilesModulesSignalsTasksFunctionsHelp
module
[Up: MathLock KeySummer][Up: KeySummer_TB DUT]
KeySummerIndex

// Adds keypad values; issues signals to indicate when correct
// number of keys have been pressed and whether the key
// sequence is acceptable to open the lock.
// NOTE: If 'ClearSum' and 'AddKey' are simultaneously asserted,
// then 'ClearSum' takes precedence.

(
// Clock and reset:
iG$MasterClock,		// Master clock
iG$MasterReset,		// Master reset (active high)

// Data inputs:
iD$KeyValue,			// Key value (4 bits)

// Control point signals from controller:
iC$AddKey,			// Add key value to sum
iC$ClearSum,			// Clear the sum

// Data outputs:
oD$KeySum,			// Sum of key values
oD$KeysPressed,		// Number of keys pressed

// Condition signals to controller:
oS$SumIsCorrect,	// Indicates when sum is valid
oS$KeyPressingIsFinished	// Indicates when correct number of keys
								// have been pressed
);

parameter pN$ValidSum = 42;		// Valid sum to open lock
parameter pN$KeyPresses = 6;	// Number of keys in valid sequence

input	iG$MasterClock;
input	iG$MasterReset;
input	[3:0]	iD$KeyValue;
input iC$AddKey;
input iC$ClearSum;

output [5:0] oD$KeySum;
output [2:0] oD$KeysPressed;
output oS$SumIsCorrect;
output oS$KeyPressingIsFinished;

reg [5:0] oD$KeySum;
reg [2:0] oD$KeysPressed;

always @ (posedge iG$MasterClock or posedge iG$MasterReset)
	if (iG$MasterReset) begin
		oD$KeySum <= 0;
		oD$KeysPressed <= 0;
	end
	else
		if (iC$ClearSum) begin
			oD$KeySum <= 0;
			oD$KeysPressed <= 0;
		end
		else if (iC$AddKey) begin
			oD$KeySum <= oD$KeySum + iD$KeyValue;
			oD$KeysPressed <= oD$KeysPressed + 1;
		end

assign oS$SumIsCorrect = (oD$KeySum == pN$ValidSum);
assign oS$KeyPressingIsFinished = (oD$KeysPressed == pN$KeyPresses);

endmodule


HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Thu Jan 16 14:38:01 2003
From: keysummer.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help