module IntervalTimer_TB;

reg	iG$MasterClock;
reg	iG$MasterReset;
reg 	iC$InitializeTimer;
reg 	iC$EnableTimer;

wire 	oS$IntervalIsComplete;
wire 	[4:0] oD$IntervalTimer;

parameter MaxChars = 18;
reg [8*MaxChars-1 : 0] Comment;

IntervalTimer DUT (
	.iG$MasterClock (iG$MasterClock),
	.iG$MasterReset (iG$MasterReset),
	.iC$InitializeTimer (iC$InitializeTimer),
	.iC$EnableTimer (iC$EnableTimer),

	.oS$IntervalIsComplete (oS$IntervalIsComplete),
	.oD$IntervalTimer (oD$IntervalTimer)
);

initial begin
	Comment = "Reset";
	iG$MasterClock = 0;
	iG$MasterReset = 1;
 	iC$InitializeTimer = 0;
 	iC$EnableTimer = 0;

	// Take out of reset
	#10 iG$MasterReset = 0;

	// Enable timer after a few cycles (to verify that timer
	// waits for enabling signal)
	#30 iC$EnableTimer = 1;
	Comment = "Timer Enabled";

	// Wait for end of interval
	wait (oS$IntervalIsComplete) ;
	
	// Initialize timer
	#10 iC$InitializeTimer = 1;
	Comment = "Timer Initialized";

	#50 $finish;
end

always #5 iG$MasterClock = ~iG$MasterClock;

endmodule