Dr. Daniel Chang’s areas of interest include computer architecture, memory systems, 3D integration technology, high-performance computing (HPC), generative artificial intelligence, low-power computing systems, and digital system design. He also advises three student organizations on campus: the student chapter of the Institute of Electrical and Electronics Engineers (IEEE), the ECE honor society Eta Kappa Nu (HKN), and the Magic: The Gathering club.
Academic Degrees
- PhD, University of Wisconsin-Madison, 2013
- MS, University of Wisconsin-Madison, 2008
- BS, University of Illinois at Urbana-Champaign, 2002
Awards & Honors
- 2025 Dean's Outstanding Teacher Award
- 2015 Outstanding Organization Advisor
Research Interests
- Modeling future computer architectures targeting high performance computing and generative artificial intelligence.
- Working with undergraduate students to develop a specialized computer architecture for modeling neurons and a neural system.
- Improving student learning in introductory computer engineering courses.
- Improving student experiences in freshmen-level ECE courses to help retention.
Select Publications & Presentations
- Taylor, E.M., and Chang, D.W., "Studying victim caches in GPUs," in 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), IEEE, 2018
- Daruwalla, K., Olivero, N., Pluger, A., Rao, S., Chang, D. W., & Simoni, M. "A quantitative analysis of the performance of computing architectures used in neural simulations," Journal of Neuroscience Methods, 311, 57-66, 2018
- Chang, D.W. "Improving student confidence and retention using an introductory computer engineering course." in 2017 ASEE Annual Conference & Exposition. 2017
- Berry C.A., Chang, D.W., and Miller, C., "From LEGO to Arduino: Enhancement of ECE Freshman Design with Practical Applications," Proceedings of the 2016 American Society of Engineering Education Conference, New Orleans, 2016
- Chang, D.W., et. al., “Dynamic Bandwidth Scaling for Embedded DSPs with 3D-Stacked DRAM and Wide I/Os,” Proceedings of the International Conference on Computer-Aided Design, San Jose, Calif., 2013
- Chang, D.W., et. al., “Reevaluating the Latency Claims of 3D Stacked Memories,” Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2013
- Chang, D.W., Kim, N.S. and Schulte, M.J., “Analyzing the Performance and Energy Impact of 3D Memory Integration on Embedded DSPs,” Proceedings of the International Conference of Embedded Computer Systems, Samos, Greece, 2011
- Chang, D.W., et al. "ERCBench: An open-source benchmark suite for embedded and reconfigurable computing." 2010 International Conference on Field Programmable Logic and Applications. IEEE, 2010.
Teaching Interests
- Computer architecture
- Memory systems
- 3D integration technology
- High Performance Computing
- Digital system design
- Design for first-year students