Verilog

Verilog Boilerplate Generator

NOTE: This tool is now obsolete. Please use the new version called Verilog Template Maker.

Generates a circuit module template and an associated testbench template. Copy the resulting Verilog file from the browser by selecting all text (Ctrl-A) and pasting into your own file. Hit your browser's "back" button to return from the Verilog file display.

Module Name: Valid characters besides alpha-numerics include '$' and '_'.
Module Description: Enter a one-sentence description of your system
Input port names, widths, and descriptions: Port names must start with a letter. They can be any length. Do not* end bus names with a number.* Enter names from the top of the list and work down. Do not leave blanks.
Output port names, widths, and descriptions: Port names must start with a letter. They can be any length. Do not* end bus names with a number.* Enter names from the top of the list and work down. Do not leave blanks.

Select the templates you need using the checkboxes below. I suggest that you first submit the form for the circuit module alone, then back up to this form (use your browser's "back" button) and resubmit for the testbench alone. You may check both boxes if you want both modules in the same file.

Selecting the "UCF" (user constraints file) template option will override the module template options, so you will receive only the UCF text.

Circuit module template
Testbench module template

UCF template (for Xilinx Foundation Series FPGA software)