IP Modules -- UART

Overview

In this lab you will gain experience working with pre-designed IP (Intellectual Property). The specific IP in this project is a UART, or Universal Asynchronous Receive-Transmitter. The UART enables communication between a PC and your FPGA-based system. The IP is written in VHDL and is optimized for implementation in a Xilinx FPGA, so the lab also gives you practice with a mixed-language project.

Objectives

Software

IP Modules

Equipment

Documents

Activities

NOTE 1: For each of the three circuits below, develop a system block diagram that includes:

NOTE 2: Your design must conform to ALL of the Synthesis Design Rules, including the naming conventions at the bottom of the document (use at least the minimal format of r_, w_, p_, etc.).

1. Familiarize yourself with the UART transmitter and receiver macros (refer to the PDF file in the zip file distribution)

2. Stand-alone UART transmitter: Design a circuit to exercise the UART_Tx module as a stand-alone device. For example, you could use a counter to apply a sequence of ASCII character codes to the module at a fixed rate, and then watch the resulting characters printing on the HyperTerminal window. Character code patterns could be as simple as an ascending sequence, or you could use a counter to drive a look-up table (combinational circuit or ROM) to display a message. As another example, you could use the PS/2 interface module you designed in an earlier lab as the source of 8-bit values, and then convert them to ASCII characters before sending them to the UART_Tx module.
   
   NOTE 1: Setting up a complete testbench for this (and the following circuits) is challenging, since you would need to emulate the serial port of your computer. While this is certainly possible, the effort required is not warranted for this lab.
   
   NOTE 2: You need not do anything with the buffer status indicators ("buffer full" and "buffer half full") for this circuit.

3. Stand-alone UART receiver: Design a circuit to exercise the UART_Rx module as a stand-alone device. For example, your circuit could accept keypresses from HyperTerminal (by activating the 'read_buffer' input at a slow rate, say one or two hertz) and interpret them in some way using the four-digit seven-segment display or discrete LEDs. Connect the three status signals ("buffer_data_preset", etc.) to discrete LEDs on the DIO4 board.

4. Full UART: Design a circuit to combine the UART_Tx and UART_Rx modules. For example, connect the UART_Rx output to the UART_Tx input so that characters typed at the HyperTerminal will be echoed back as-is, or perhaps modified using some rule such as “add one” to the ASCII character code. HINT: It is possible to do this part with wires only (at least the echo technique).

5. Confirm that all designs work properly on the Digilent D2SB/DIO4/SIO1 or D2E/DIO1 board combo.

6. Create a distinct bitfile for each of the three circuits, then demonstrate all three at one time for the instructor.

Tips and Info

1. ASCII character codes are listed at http://www.asciitable.com (one example of many on-line tables).

2. Verilog supports ASCII. Use double-quotes around a character like this: "A". The result is an 8-bit constant with value 8'h41.

3. Use HyperTerminal to set up a COM port connection and to see a list of valid baud rates.

4. Add all the Verilog and VHDL modules to your Xilinx project as you normally add source files, but only add the files that you need. For example, when doing the UART_Tx stand-alone circuit you should have the following: (1) top-level Verilog module, (2) freqdiv.v, (3) uart_tx.vhd, (4) bbfifo_16x8.vhd, and (5) kcuart_tx.vhd.

5. Only instantiate the VHDL modules ‘uart_tx’ and/or ‘uart_rx’ in your top-level design (the two sub-modules are already instantiated); use the same Verilog instantiation technique as you have done in the past

6. I developed the parameterized frequency divider for this project to make it easy to gear-down the 50MHz clock to whatever frequency you need. Typical ‘defparam’ statement is ‘defparam RefID.Divisor = 50_000_000 / 1_000;’ with the second value indicating the desired frequency. See the documentation at the top of freqdiv.v for the instantiation template.

7. The D2E board contains an RS-232 transceiver chip and 9-pin serial port connector; use the D2E UCF generator to obtain the correct pin numbers for the RS-232 connector.

8. You may find it helpful to include a low-frequency "blinker" circuit that operates the single LED on the D2SB (or D2E) board. The blinking LED serves as a "heartbeat" and will tell you that your bitstream file has properly configured the FPGA, especially when you have no other visual indicators. Get the Blinker.v module (look in the "IP Modules" folder).

9. Use HyperTerminal configured for your selected baud rate, and set “Flow Control” to “None” (this is important!)

10. HyperTerminal will only display characters when it receives them from the COM port. Therefore you should not expect to see anything on the screen when you are testing your UART_Rx stand-alone circuit.

11. Use the serial port tester bitfiles if you need a "sanity check" of your equipment; see PLD Oasis > Hardware.

Deliverables

1. Brief cover memo that describes your three designs

2. Block diagram drawings of each of your three circuit designs

3. Hardcopy of all synthesizable Verilog files that you created yourself

4. Demonstration of your design to instructor (obtain initials)

Deliverables

1. I/O block diagrams for your PS/2 and FIFO modules, and the top-level module

2. System block diagram for your top-level module

3. Hardcopy of mixed-signal oscilloscope PS/2 waveforms

4. Waveform plots of each of your three functional verifications

5. Hardcopy of all Verilog code produced

6. Memo detailing your design process and results. Describe the operating principles of your PS/2 and FIFO modules.

7. Demonstration of your design to instructor (obtain initials)

Due Date

Beginning of lab one week from today