LED Dimmer for Digilent Board

Introduction

This lab will continue your practice with the Digilent D2SB/DIO4 board combination, extending the complexity to include sequential logic design. The practical end result of this lab will be a technique to vary the apparent intensity of the discrete LEDs.

Objectives

Software

Equipment

Documents

Activities

Recommended: Install WebPack and ModelSim on your own computer system; see above for the link to instructions.

1. Review the step-by-step instructions file "From Concept to Bitstream" if you are still experiencing any problems using the Xilinx CAD tools.

2. Read the Synthesis Design Rules document. Your design must conform to ALL of the listed design rules except the signal naming conventions at the bottom of the document.

3. Reflect on how varying the "on" time of a periodic rectangular waveform will result in an apparent change in the intensity of the LED. This technique for intensity variation is called pulse width modulation, or PWM. Choose a frequency that is above the "flicker fusion frequency" of the human visual system, which is about 30 Hz. The higher the frequency the more stable the appearance of the LED, but a frequency that is too high will not allow the LED to turn on and off properly.

4. Design a circuit module that will meet the following minimum requirements:

   1. Accepts eight inputs to be passed to the eight discrete LEDs

   2. Accepts a three-bit integer that represents the desired intensity of the LEDs (0 corresponds to completely off, 7 corresponds to maximum possible, with linear variation in between)

   3. Operates from 50 MHz clock source

   4. Includes master reset from pushbutton

5. Choose one or more of the following embellishments:

   1. Accepts LED and/or intensity inputs from combination of switches and pushbuttons

   2. Accepts LED  and/or intensity inputs from a source internal to the FPGA (e.g., counter, shift register, bit rotater, etc.)

   3. Accepts LED and/or intensity inputs from parallel port

   4. Displays presently-selected intensity value on one of the seven-segment display digits

   5. Anything else you think would be interesting

6. Produce a detailed hardware diagram that illustrates the circuit you will place into the FPGA.

7. Write a Verilog description that translates your diagram from the previous step.

8. Debug your circuit using a testbench Verilog file and behavioral simulation.

9. Create a UCF file using the D2SB/DIO4 UCF generator spreadsheets.

10. Use the Xilinx WebPack tool to create an FPGA bitstream file for your design.

11. Test and evaluate your design on the D2SB/DIO4 board.

Deliverables

1. Brief memo that describes your design process and results (include one campus mail box number at the top of the memo). Include the following attachments:

   1. Block diagram or circuit diagram of your design

   2. Behavioral simulation results (waveform plot, with handwritten annotations to explain how you know that your circuit is working properly)

   3. Verilog synthesizable .v file

   4. Verilog testbench .v file

   5. UCF file
       

2. Demonstration of finished project to instructor (obtain initials)

Due Date

Beginning of next week's lab