Practice with Digilent Board and CAD Tools

Introduction

This lab will reacquaint you with the CAD tools and equipment used to design, simulate, and implement FPGA-based designs, and will also give you some exposure to the Digilent D2SB/DIO4 board combination.

Objectives

Software

Equipment

Documents

Activities

Recommended: Install WebPack and ModelSim on your own computer system; see above for the link to instructions.

1. Review the step-by-step instructions file "From Concept to Bitstream" .

2. Review the Synthesis Design Rules document. You may ignore (for now) the sections about signal naming conventions, but pay close attention to the remaining sections.

3. Design a simple combinational or sequential circuit and describe it in Verilog. The circuit should do something interesting or useful with the input and output devices on the DIO4 board.
   
   NOTE: If you plan to use any of the eight discrete LEDs, you must ensure that the transparent latch between the FPGA and LEDs is permanently enabled. Create a single port pin that is permanently driven high (e.g., include a line such as assign LEDenable = 1;), and enter this name into the UCF generator spreadsheet cell called "Discrete LED latch gate".
    

4. Debug your circuit using a testbench Verilog file and behavioral simulation.

5. Create a UCF file using the D2SB/DIO4 UCF generator spreadsheets.

6. Use the Xilinx WebPack tool to create an FPGA bitstream file for your design.

7. Test and evaluate your design on the D2SB/DIO4 board.

Deliverables

1. Brief memo that describes your design process and results (include one campus mail box number at the top of the memo). Include the following attachments:
   - Block diagram or circuit diagram of your design
   - Behavioral simulation results (waveform plot)
   - Verilog synthesizable .v file
   - Verilog testbench .v file
   - UCF file
    

2. Demonstration of finished project to instructor (obtain initials)

Due Date

Beginning of next week's lab