![]() ece533 | doering | ece labs | ece | rhit |
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Gain familiarity with Digilent D2SB/DIO4 FPGA prototyping board |
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Gain familiarity with CAD tools |
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Implement a simple circuit |
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NC-Sim or ModelSim Verilog behavioral simulator |
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Xilinx WebPack ISE 6.3 FPGA implementation tools |
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Digilent D2SB/DIO4 board combination |
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Parallel port cable |
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DC power supply |
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PLD Oasis > Tutorials/Documents > From Concept to Bitstream -- A "How-To" Guide for Xilinx FPGAs |
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PLD Oasis > Software > Installation instructions for version 6.1 and ModelSim XE-II 5.7 plug-in (works for WebPack ISE version 6.3, too) |
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PLD Oasis > Software > UCF Generators for D2SB/DIO4 board set |
Recommended: Install WebPack and ModelSim on your own computer system; see above for the link to instructions.
Review the step-by-step instructions file "From Concept to Bitstream" .
Review the Synthesis Design Rules document. You may ignore (for now) the sections about signal naming conventions, but pay close attention to the remaining sections.
Design a simple combinational or sequential circuit and describe
it in Verilog. The circuit should do something interesting or useful with the
input and output devices on the DIO4 board.
NOTE: If you plan to use any of the eight discrete LEDs, you must
ensure that the transparent latch between the FPGA and LEDs is permanently
enabled. Create a single port pin that is permanently driven high (e.g., include
a line such as assign LEDenable = 1;), and enter
this name into the UCF generator spreadsheet cell called "Discrete LED latch
gate".
Debug your circuit using a testbench Verilog file and behavioral simulation.
Create a UCF file using the D2SB/DIO4 UCF generator spreadsheets.
Use the Xilinx WebPack tool to create an FPGA bitstream file for your design.
Test and evaluate your design on the D2SB/DIO4 board.
Brief memo that describes your design process and results
(include one campus mail box number at the top of the memo).
Include the following attachments:
- Block diagram or circuit diagram of your design
- Behavioral simulation results (waveform plot)
- Verilog synthesizable .v file
- Verilog testbench .v file
- UCF file
Demonstration of finished project to instructor (obtain initials)
Beginning of next week's lab
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