Problem Statement

A state diagram for a finite state machine controller is given (see PDF file). Write a synthesizable Verilog module that implements the state machine, and write a testbench Verilog module that exercises each path of the state diagram.

Order your simulation waveforms from top to bottom as follows:

1. Clock
2. Reset
3. Inputs (BEGIN, MODE)
4. Outputs (FINISHED, PULSE, FURP, BEEP)
5. State register value

Deliverables

1. Hardcopy of both Verilog modules
2. Hardcopy of simulator waveforms, with handwritten annotations to explain why the waveforms confirm the correct operation of your state machine

Optional

Use technique described in PLD Oasis > Tutorials/Documents > Verilog Examples > fsm_example2_TB.v to make the simulator display the state register state codes as text labels.