Step 1 -- Create your conceptual design:

	Step 1a -- Create conceptual design for synthesizable circuit or system (2:15)
	Step 1b -- Create test plan for circuit (2:13)

Step 2 -- Create the template Verilog files (2:18)

Step 3 -- Enter your Verilog circuit descriptions:

	Step 3a -- Translate your circuit design into a synthesizable Verilog description (2:38)
	Step 3b -- Translate your test plan into a Verilog testbench (1:18)
	Steb 3c -- Enter your Verilog descriptions (includes Verilog Template Maker) (3:21)

Step 4 -- Perform functional verification (simulation) (3:57)

Step 5 -- Synthesize your design to a bitstream (.bit) file (5.24)

Step 6 -- Download the .bit file to the FPGA (Spartan-3 board) (0:54)

Basic schematic-entry techniques (8:08)
1. Introduction 2. Create new project 3. Create new schematic page 4. Detach schematic window to maximize size 5. Select and place components 6. Adjust view (zoom in and out) 7. Place additional components 8. Connect components with wires 9. Place I/O markers 10. Adjust I/O names 11. Place a title block 12. Re-attach the schematic window to Project Navigator 13. Synthesize the circuit 14. View synthesized circuit as a block diagram 15. View synthesized design as Xilinx-specific technology 16. Assign FPGA pin numbers to I/O markers

Top-level schematic with sub-level schematics (4:59)
1. Introduction 2. Two example subcircuits 3. Create symbols from schematic-based circuits 4. Create new top-level schematic 5. Place symbols for subcircuits 6. Wire subcircuits together 7. Add I/O port names 8. Add I/O markers 9. Navigate through the subcircuit hierarchy 10. Push into a symbol 11. Pop back up from the symbol 12. Push into symbol (alternate method)

Top-level schematic with both HDL (Verilog) and schematics as sub-level modules (4:23)
1. Introduction 2. Begin with schematic and subcircuits 3. Add a pre-written Verilog module 4. Create a symbol for the Verilog module 5. Place the symbol for the Verilog module 6. Edit the symbol to re-arrange pins 7. Update schematic with modified symbol 8. Re-wire the circuit 9. Synthesize the design

Top-level HDL with both HDL and schematics as sub-level modules (7:55)
1. Introduction 2. Begin with empty top-level Verilog module 3. Add an existing schematic circuit 4. Add an existing Verilog module 5. Create instantiation template for schematic circuit 6. Insert template into top-level module 7. Create instantiation template for Verilog circuit 8. Insert template into top-level module 9. Connect instantiation templates by ports and wires10. Synthesize top-level module11. View hardware diagram 12. Observe wiring errors revealed by RTL viewer 13. Trouble-shoot original design 14. Correct the design entry errors 15. Re-synthesize the top-level module 16. View corrected design 17. View technology schematic 18. View LUT definitions: 19. ... as schematic, 20. ... as truth table, and 21. ... as K-map.

Top-level schematic with 130.v library components (12:23)
1. Introduction 2. Begin with new project 3. Create a new schematic 4. Add the 130.v library 5. Move 130.v modules to Verilog library view 6. Select component from library... 7. ... and create a symbol for it 8. Repeat for additional components as needed 9. Place components into schematic drawing 10. View details of created symbols 11. Connect bus-style ports together 12. Create clock and reset input connections 13. Create bus-style input port 14. Place bus tap for subrange of input bus 15. Place bus tap for single wire of bus 16. Place components from Xilinx library 17. Finish wiring the circuit 18. Synthesize the design for first time 19. Correct output port name error 20. Synthesize second time 21. Examine warning about deleted module 22. Identify wiring error and correct it 23. Synthesize corrected circuit

Design and verify an HDL-based (Verilog) finite state machine (FSM) (34:00)
1. Introduction 2. FSM specifications 3. Create state transition diagram 4. Begin creating hardware diagram 5. Create specific hardware diagram 6. Create input/output symbol 7. Create test plan 8. Use VTM to create template .v files 9. Download 130.v library file to folder 10. Place components into synthesizable module (use instantiation template spreadsheet) 11. Enter testbench input patterns from testplan 12. Simulate in Cadence 13. Order signals in related groups 14. Begin troubleshooting process 15. View design as hardware block diagram in Cadence 16. Troubleshoot design entry error related to next-state decoder 17. Design error found! 18. Correct the design error 19. Re-simulate to confirm correct operation 20. Create named groups for waveform traces 21. Save waveform work to command script 22. Run command script to re-generate waveforms in correct order

Design and verify a schematic-based finite state machine

	Convert state diagram into hardware diagram (4:20) 1. Draw state register 2. Create next-state decoder 3. Create output decoder 4. Connect to global resources (clock, reset) 5. Define asynchronous reset state 6. Identify primary inputs and outputs 7. Identify bus widths
	Use 'symgen' to create schematic symbols (4:50) 1. Begin with new Xilinx project 2. Ensure '130.v' and ‘symgen.exe’ files are in project folder 3. Start 'symgen' application 4. Create register symbol for state register 5. Create "big MUX" 6. Create constant operators 7. Create comparators
	Enter the schematic into Xilinx (7:22) 1. View files created by ‘symgen’ 2. Create new schematic source 3. Place 'symgen'-created symbols 4. Connect symbols with wires 5. Name the primary I/O nets 6. Add I/O markers 7. Connect register clock and reset 8. Create clock and reset input ports
	Simulate the schematic design in Cadence (9:50) 1. Choose I/O port names to match Verilog Template Maker (VTM) 2. Set the register's "clock enable" to a logic 1 3. Bring out FSM "state" and "next state" busses 4. Create testbench template 5. Create input waveform to test all possible paths in state diagram 6. Create Verilog module from schematic (.vf file) 7. Start NC-Sim 8. Set design directory to the Xilinx project folder 9. Create CDS.LIB file 10. Include *.vf in filter list 11. Select all Verilog files associated with the schematic 12. Compile all Verilog files 13. Elaborate the testbench module 14. Launch the testbench simulation 15. Choose waveforms to display 16. Run the simulation 17. Confirm correct behavior of FSM
	Prepare the design for implementation on the Spartan-3 board (16:10) 1. Save simulation-only schematic (optional) 2. Remove simulation-only components 3. Create symbols for selected 130.v library components 4. Place the selected 130.v library components 5. Connect components to global resources (clock, reset) 6. Connect the switch debouncer to primary input "A" 7. Connect the "clock enabler" to register 8. Finish remaining "clock enabler" connections 9. Connect "DisplayHex" outputs 10. Create operators to promote 2-bit bus to 8-bit bus 11. Connect "present state" bus to right side of display 12. Connect "next state" bus to left side of display 13. Add associated .v files for each 'symgen' symbol 14. Assign pins to Spartan-3 resources (create UCF file)
	Synthesize to a bitstream file (and interpret the synthesis warning messages) (3:59) 1. Start synthesis process 2. Determine which warnings to ignore...  3. ... and which warnings to pursue further 4. Discuss "removed logic" 5. Continue with implementation process 6. Create the bitstream file

Design a schematic-based FSM using text-based next-state decoder (NSD) and output decoder (OD) -- a simpler way to implement complex state diagrams (21:00)
1.Review the example state diagram 2.Construct prototype state machine 3.Review diagram for number of inputs and outputs 4.Begin schematic diagram 5.Set color scheme 6.Create 'symgen' symbol for register 7.Create symbol for NSD 8.Create symbol for OD 9.Place the symbols 10.Create clock and reset inputs 11.Create inputs A, B, and C 12.Create bus taps to merge inputs 13.Create buffers for name aliases 14.Repeat activities for outputs 15.Check schematic for errors 16.Add Verilog sources for 'symgen' symbols 17.Enter text for OD 18.Enter text for NSD 19.Create name aliases 20.example: Unconditional transition 21.example: conditional transition, one variable 22.example: conditional transition, mixture of single and multiple variables 23.example: use of "otherwise" technique 24.example: several exit paths 25.example: trap state 26.Synthesize to confirm correct syntax