Summary
It is rather easy to write a Verilog description that simulates fine, but
produces cryptic error messages during the implementation (synthesis) phase.
This document lists common problems and provides troubleshooting tips to resolve
them (the links are simply bookmarks on this web page):
Multiple outputs driving a common net
- Description
-
Multiple circuit outputs (gates or flip-flops) are tied together. This is
not acceptable from an electrical standpoint.
- Symptoms
-
Synthesis error message: “Net nnn has multiple drivers”
- Cause
-
The same output signal name appears in more than one ‘always’ block
- Troubleshooting
-
Search for the net named in the error message, and identify all the
‘always’ blocks where the name appears
- Solution
-
Ensure that the output signal is contained within a single ‘always’ block
- Comments
-
This problem is symptomatic of a sequential programming mindset. In order
to break this mindset, focus your attention exclusively on a single device (a
counter, for example), and write one ‘always’ block that describes the entire
behavior of the counter (its behavior on asynchronous reset, and its normal
behavior).
Inferred latch
- Description
-
A latch (similar to a flip-flop, except it is level-triggered instead of
edge-triggered) has been placed at the output of what is intended to be a
purely combinational circuit.
- Symptoms
-
Synthesis warning message: “Inferred latch…”
- Cause
-
Combinational logic that does not fully specify the output behavior for
all possible input combinations
- Troubleshooting
-
First look for all combinational circuit ‘always’ blocks (those that do
not have edge qualifiers). Inside these blocks look for ‘if’ statements that
do not have an ‘else’, and ‘case’ statements that do not have a ‘default’.
- Solution
-
Fix the ‘if’ or ‘case’ statement, or use technique of first setting all
outputs to a nominal value before the conditional statements.
- Comments
-
Inserting unintended memory devices in your design can cause operational
problems in hardware, and will also cause problems in the implementation step.
Ignored synthesis warning messages
- Description
-
You see one or more warnings during synthesis step, but ignore them and
proceed to implementation
- Symptoms
-
Yellow warnings appear in synthesis, followed by red error messages in
implementation
- Cause
-
Synthesis warnings mean that something is not correct. The problem may not
be severe enough to be called an “error” that stops synthesis, but it
effectively is an error for you because your design will not implement
properly.
- Troubleshooting
-
Same procedure as 'Solution' next
- Solution
-
Start with first synthesis warning and solve that problem first. Often
many (or all) successive warnings stem from the first cited problem. If you
still have warnings, or possibly a totally new set of warnings, still tackle
the first warning first.
- Comments
-
The only synthesis warnings that can be safely ignored are those that you
understand completely. For example, if you have intentionally connected an
output pin to an input pin, you will see a warning about a “feed-through net”.
Synthesis tool removes portions of your design
- Description
-
The synthesis tool always optimizes your design, and will eliminate any
apparently unused portions of your circuit.
- Symptoms
-
Synthesis warning message about “unreachable code” (as in an ‘if-else’
statement with a conditional test that is always false) or “unlinked cell,” or
“removing pads.” Implementation error message saying named nets in UCF file
are not found in your design.
- Cause
-
If the synthesis tool concludes that some part of your circuit is useless
(for example, its output does not connect to an external port and does not get
used by any other internal device), then the tool removes the circuit and
backtracks to remove any previous circuits that are only associated with the
useless circuit. Eventually this can cause input ports to get removed as well.
- Troubleshooting
-
Same procedure as 'Solution' next
- Solution
-
Focus your attention on the named files and devices in the synthesis
warning messages. Look for device outputs that do not connect to anything, or
that connect to circuits that do nothing.
- Comments
-
This is one of the more challenging problems to resolve!
Mixed edge-sensitive and level-sensitive signals in
‘always’ block sensitivity list
- Description
-
Your ‘always’ block begins with something like: ‘always @ (posedge
FirstSignal or SecondSignal)’
- Symptoms
-
Synthesis tools will generate specific warning
- Cause
-
If your circuit is supposed to be sequential, then you must use an edge
qualifier (posedge or negedge) on both signals in the sensitivity list
- Troubleshooting
-
- Solution
-
- Comments
-
The faulty ‘always’ block will simulate just fine, but it won’t
synthesize.
Failure to name all inputs in sensitivity list
for a combinational circuit
- Description
-
Combinational circuits described by an ‘always’ block must list all inputs
in the sensitivity list
- Symptoms
-
Simulation will show a circuit output that is apparently unresponsive to
one or more of the inputs. Synthesis will generate a warning about an
“untested input”.
- Cause
-
Simulator does not update an output unless the input is included in the
sensitivity list; it effectively is blind to changes in that input.
- Troubleshooting
-
Look at all signals on the right-hand side of all assignments in the
‘always’ block, and look for signal names that do not show up in the
sensitivity list.
- Solution
-
Ensure that every signal is included in the sensitivity list.
- Comments
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