FPGA | XC4010XL | XS40 | Foundation Series | Schematic

This section is still under development...

NOTE: Schematic-based designs are generally less efficient to enter and maintain than HDL-based designs. Please refer to the FPGA/Verilog Design Flow.

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Page last updated December 21, 1999. Feedback goes to Ed.Doering@Rose-Hulman.Edu.