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CPLD | MACH4 64/32 | Vantis ISP Board | Vantis Design Direct |
Verilog
Step 6: Select Verilog simulator, or go back to previous step:
- Simucad Silos
III (demo version)
- -- Simulates Verilog description directly, with no need to first synthesize a
netlist
-- Uses Verilog "testbench" file to design input stimulus (often more efficient
in the long run compared to interactive graphical methods)
-- Output waveforms update immediately by pressing "Alt-F5" (reloads,
recompiles, and resimulates Verilog files from a single keystroke; facilitates rapid
debugging)
-- Demo version is limited in the size of the project that can be simulated, but is
otherwise fully functional (i.e., project files and stimulus files can be saved)
- SynaptiCAD VeriLogger
PRO (demo version)
- -- Simulates Verilog description directly, with no need to first synthesize a
netlist
-- Features graphical interface to interactively design input stimulus
-- Output waveforms update immediately in response to changes in input stimulus patterns
(facilitates rapid debugging)
-- Demo version permits read/write of Verilog (.v) files up to 1000 lines long, but does
not permit read/write of project or stimulus files
-- Best for quickly testing small code fragments
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