CPLD | MACH4 64/32 | Vantis ISP Board | Vantis Design Direct

Step 5: Select design entry method, or go back to previous step:

ABEL

-- Hardware design language (HDL) approach
-- The course text (Wakerly) includes numerous examples

Schematic

-- Graphical method to place and connect components

Verilog

-- Hardware description language (HDL) approach

Page last updated December 21, 1999. Feedback goes to Ed.Doering@Rose-Hulman.Edu.