;****************************************************************************** ;* TMS320C6x ANSI C Codegen Version 4.10 Beta (May 4 2001) * ;* Date/Time created: Tue May 29 12:12:02 2001 * ;****************************************************************************** ;****************************************************************************** ;* GLOBAL FILE PARAMETERS * ;* * ;* Architecture : TMS320C671x * ;* Optimization : Enabled at level 3 * ;* Optimizing for : Speed * ;* Based on options: -o3, no -ms * ;* Endian : Little * ;* Interrupt Thrshld : Disabled * ;* Memory Model : Large * ;* Calls to RTS : Far * ;* Pipelining : Enabled * ;* Speculative Load : Disabled * ;* Memory Aliases : Presume are aliases (pessimistic) * ;* Debug Info : No Debug Info * ;* * ;****************************************************************************** .asg A15, FP .asg B14, DP .asg B15, SP .global $bss .sect ".cinit" .align 8 .field 4,32 .field _ledVal+0,32 .field 0,32 ; _ledVal @ 0 .sect ".text" _ledVal: .usect .far,4,4 .sect ".cinit" .align 8 .field 4,32 .field _initialized$1+0,32 .field 0,32 ; _initialized$1 @ 0 .sect ".text" _initialized$1: .usect .far,4,4 ; c:\ti\c6000\cgtools\bin\opt6x.exe -qq -v6711 -O3 C:\WINDOWS\TEMP\TI506495_2 C:\WINDOWS\TEMP\TI506495_4 .sect ".text:__LED_init" .clink .global __LED_init ;****************************************************************************** ;* FUNCTION NAME: __LED_init * ;* * ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, * ;* B7,B8,B9,SP * ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, * ;* B7,B8,B9,SP * ;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * ;****************************************************************************** __LED_init: ;** --------------------------------------------------------------------------* MVKL .S2 _initialized$1,B5 ; |81| MVKH .S2 _initialized$1,B5 ; |81| LDW .D2T1 *B5,A1 ; |81| MVKL .S1 0x1800004,A0 ; |79| MVKH .S1 0x1800004,A0 ; |79| LDW .D1T2 *A0,B4 ; |79| MVKL .S2 0x1800004,B5 ; |85| [ A1] B .S1 L5 ; |81| MVK .S1 240,A4 ; |86| MVK .S1 32,A3 ; |86| CLR .S2 B4,4,7,B6 ; |85| MVKH .S2 0x1800004,B5 ; |85| || MVKL .S1 0x1800004,A0 ; |86| SET .S2 B6,5,5,B6 ; |85| || MVKH .S1 0x1800004,A0 ; |86| || STW .D2T2 B3,*SP--(8) ; |77| ; BRANCH OCCURS ; |81| ;** --------------------------------------------------------------------------* STW .D2T2 B6,*B5 ; |85| LDW .D1T1 *A0,A0 ; |86| NOP 4 AND .S1 A4,A0,A0 ; |86| CMPEQ .L1 A0,A3,A1 ; |86| [ A1] B .S1 L4 ; |86| MVK .S1 0xf0,A5 ; |86| [ A1] MVKL .S2 _ledVal,B5 ; |90| || MVK .S1 0x20,A4 ; |86| [!A1] MVKL .S1 0x1800004,A3 ; (P) |86| [!A1] MVKH .S1 0x1800004,A3 ; (P) |86| [!A1] LDW .D1T1 *A3,A0 ; (P) ^ |86| ; BRANCH OCCURS ; |86| ;** --------------------------------------------------------------------------* MVK .S2 0x1,B0 NOP 3 AND .S1 A5,A0,A3 ; (P) ^ |86| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 86 ;* Loop opening brace source line : 0 ;* Loop closing brace source line : 0 ;* Known Minimum Trip Count : 1 ;* Known Max Trip Count Factor : 1 ;* Loop Carried Dependency Bound(^) : 8 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 0 ;* .S units 2* 1 ;* .D units 1 0 ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 1 0 ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 1 0 (.L or .S unit) ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 2* 1 ;* Bound(.L .S .D .LS .LSD) 2* 1 ;* ;* Searching for software pipeline schedule at ... ;* ii = 8 Schedule found with 2 iterations in parallel ;* done ;* ;* Loop is interruptible ;* Collapsed epilog stages : 1 ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L1: ; PIPED LOOP PROLOG ;** --------------------------------------------------------------------------* L2: ; PIPED LOOP KERNEL CMPEQ .L1 A3,A4,A1 ; ^ |86| || MVKL .S1 0x1800004,A3 ; @|86| [ A1] ZERO .D2 B0 ; ^ || MVKH .S1 0x1800004,A3 ; @|86| [ B0] B .S2 L2 ; |86| || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |86| NOP 4 AND .S1 A5,A0,A3 ; @ ^ |86| ;** --------------------------------------------------------------------------* L3: ; PIPED LOOP EPILOG ;** --------------------------------------------------------------------------* MVKL .S2 _ledVal,B5 ; |90| ;** --------------------------------------------------------------------------* L4: MVKH .S2 _ledVal,B5 ; |90| || ZERO .D1 A0 ; |97| || MVK .S1 15,A3 ; |90| STW .D2T1 A3,*B5 ; |90| || MVKH .S1 0x90080000,A0 ; |97| LDW .D1T1 *A0,A0 ; |97| ZERO .D2 B5 ; |97| MVKH .S2 0x90080000,B5 ; |97| NOP 2 SET .S1 A0,24,27,A0 ; |97| STW .D2T1 A0,*B5 ; |97| NOP 9 NOP 3 MVKL .S1 __BOARD_init,A0 ; |102| MVKH .S1 __BOARD_init,A0 ; |102| B .S2X A0 ; |102| MVKL .S2 0x1800004,B5 ; |100| MVKL .S2 RL0,B3 ; |102| MVKH .S2 0x1800004,B5 ; |100| STW .D2T2 B4,*B5 ; |100| MVKH .S2 RL0,B3 ; |102| RL0: ; CALL OCCURS ; |102| MVKL .S2 _initialized$1,B4 ; |103| MVKH .S2 _initialized$1,B4 ; |103| || MVK .S1 1,A0 ; |103| STW .D2T1 A0,*B4 ; |103| ;** --------------------------------------------------------------------------* L5: LDW .D2T2 *++SP(8),B3 ; |105| NOP 4 B .S2 B3 ; |105| NOP 5 ; BRANCH OCCURS ; |105| .sect ".text:_LED_toggle" .clink .global _LED_toggle ;****************************************************************************** ;* FUNCTION NAME: _LED_toggle * ;* * ;* Regs Modified : A0,A1,A3,A4,A5,A6,A7,B0,B4,B5 * ;* Regs Used : A0,A1,A3,A4,A5,A6,A7,B0,B3,B4,B5 * ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * ;****************************************************************************** _LED_toggle: ;** --------------------------------------------------------------------------* MVKL .S1 0x1800004,A0 ; |162| MVKH .S1 0x1800004,A0 ; |162| LDW .D1T1 *A0,A7 ; |162| MVKL .S2 0x1800004,B4 ; |166| MVKL .S2 0x1800004,B5 ; |167| MVKH .S2 0x1800004,B4 ; |166| MVKH .S2 0x1800004,B5 ; |167| CLR .S1 A7,4,7,A0 ; |166| SET .S1 A0,5,5,A0 ; |166| STW .D2T1 A0,*B4 ; |166| LDW .D2T2 *B5,B4 ; |167| MVK .S1 240,A0 ; |167| MVK .S1 32,A3 ; |167| MV .D1 A4,A6 ; |160| MVK .S1 0x20,A4 ; |167| AND .S2X A0,B4,B4 ; |167| CMPEQ .L2X B4,A3,B0 ; |167| [ B0] B .S1 L9 ; |167| MVK .S1 0xf0,A5 ; |167| [!B0] MVKL .S1 0x1800004,A3 ; (P) |167| [!B0] MVKH .S1 0x1800004,A3 ; (P) |167| [!B0] LDW .D1T1 *A3,A0 ; (P) ^ |167| NOP 1 ; BRANCH OCCURS ; |167| ;** --------------------------------------------------------------------------* MVK .S2 0x1,B0 NOP 3 AND .S1 A5,A0,A3 ; (P) ^ |167| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 167 ;* Loop opening brace source line : 0 ;* Loop closing brace source line : 0 ;* Known Minimum Trip Count : 1 ;* Known Max Trip Count Factor : 1 ;* Loop Carried Dependency Bound(^) : 8 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 0 ;* .S units 2* 1 ;* .D units 1 0 ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 1 0 ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 1 0 (.L or .S unit) ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 2* 1 ;* Bound(.L .S .D .LS .LSD) 2* 1 ;* ;* Searching for software pipeline schedule at ... ;* ii = 8 Schedule found with 2 iterations in parallel ;* done ;* ;* Loop is interruptible ;* Collapsed epilog stages : 1 ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L6: ; PIPED LOOP PROLOG ;** --------------------------------------------------------------------------* L7: ; PIPED LOOP KERNEL CMPEQ .L1 A3,A4,A1 ; ^ |167| || MVKL .S1 0x1800004,A3 ; @|167| [ A1] ZERO .D2 B0 ; ^ || MVKH .S1 0x1800004,A3 ; @|167| [ B0] B .S2 L7 ; |167| || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |167| NOP 4 AND .S1 A5,A0,A3 ; @ ^ |167| ;** --------------------------------------------------------------------------* L8: ; PIPED LOOP EPILOG ;** --------------------------------------------------------------------------* L9: MVKL .S1 _ledVal,A0 ; |171| MVKH .S1 _ledVal,A0 ; |171| LDW .D1T1 *A0,A0 ; |171| MVKL .S2 _ledVal,B5 ; |171| MVKH .S2 _ledVal,B5 ; |171| ZERO .D2 B4 ; |174| MVKH .S2 0x90080000,B4 ; |174| XOR .S1 A0,A6,A0 ; |171| STW .D2T1 A0,*B5 ; |171| LDW .D2T2 *B4,B4 ; |174| SHL .S1 A0,24,A3 ; |174| ZERO .D1 A0 ; |174| MVKH .S1 0x90080000,A0 ; |174| NOP 1 CLR .S2 B4,24,27,B4 ; |174| OR .S2X A3,B4,B4 ; |174| STW .D1T2 B4,*A0 ; |174| NOP 9 NOP 3 B .S2 B3 ; |178| MVKL .S1 0x1800004,A0 ; |177| MVKH .S1 0x1800004,A0 ; |177| STW .D1T1 A7,*A0 ; |177| NOP 2 ; BRANCH OCCURS ; |178| .sect ".text:_LED_on" .clink .global _LED_on ;****************************************************************************** ;* FUNCTION NAME: _LED_on * ;* * ;* Regs Modified : A0,A1,A3,A4,A5,A6,B0,B4,B5,B6,B7 * ;* Regs Used : A0,A1,A3,A4,A5,A6,B0,B3,B4,B5,B6,B7 * ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * ;****************************************************************************** _LED_on: ;** --------------------------------------------------------------------------* MVKL .S1 0x1800004,A0 ; |136| MVKH .S1 0x1800004,A0 ; |136| LDW .D1T2 *A0,B4 ; |136| MVKL .S2 0x1800004,B6 ; |140| MVKL .S2 0x1800004,B5 ; |141| MVKH .S2 0x1800004,B6 ; |140| MVKH .S2 0x1800004,B5 ; |141| CLR .S2 B4,4,7,B7 ; |140| SET .S2 B7,5,5,B7 ; |140| STW .D2T2 B7,*B6 ; |140| LDW .D2T2 *B5,B5 ; |141| MVK .S1 240,A3 ; |141| MVK .S1 32,A0 ; |141| MV .D1 A4,A6 ; |134| MVK .S1 0x20,A4 ; |141| AND .L1X A3,B5,A3 ; |141| CMPEQ .L1 A3,A0,A1 ; |141| [ A1] B .S1 L13 ; |141| MVK .S1 0xf0,A5 ; |141| [!A1] MVKL .S1 0x1800004,A3 ; (P) |141| [!A1] MVKH .S1 0x1800004,A3 ; (P) |141| [!A1] LDW .D1T1 *A3,A0 ; (P) ^ |141| NOP 1 ; BRANCH OCCURS ; |141| ;** --------------------------------------------------------------------------* MVK .S2 0x1,B0 NOP 3 AND .S1 A5,A0,A3 ; (P) ^ |141| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 141 ;* Loop opening brace source line : 0 ;* Loop closing brace source line : 0 ;* Known Minimum Trip Count : 1 ;* Known Max Trip Count Factor : 1 ;* Loop Carried Dependency Bound(^) : 8 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 0 ;* .S units 2* 1 ;* .D units 1 0 ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 1 0 ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 1 0 (.L or .S unit) ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 2* 1 ;* Bound(.L .S .D .LS .LSD) 2* 1 ;* ;* Searching for software pipeline schedule at ... ;* ii = 8 Schedule found with 2 iterations in parallel ;* done ;* ;* Loop is interruptible ;* Collapsed epilog stages : 1 ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L10: ; PIPED LOOP PROLOG ;** --------------------------------------------------------------------------* L11: ; PIPED LOOP KERNEL CMPEQ .L1 A3,A4,A1 ; ^ |141| || MVKL .S1 0x1800004,A3 ; @|141| [ A1] ZERO .D2 B0 ; ^ || MVKH .S1 0x1800004,A3 ; @|141| [ B0] B .S2 L11 ; |141| || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |141| NOP 4 AND .S1 A5,A0,A3 ; @ ^ |141| ;** --------------------------------------------------------------------------* L12: ; PIPED LOOP EPILOG ;** --------------------------------------------------------------------------* L13: MVKL .S1 _ledVal,A0 ; |145| MVKH .S1 _ledVal,A0 ; |145| LDW .D1T1 *A0,A0 ; |145| NOT .L1 A6,A4 ; |145| MVKL .S1 _ledVal,A3 ; |145| MVKH .S1 _ledVal,A3 ; |145| ZERO .D2 B5 ; |152| AND .L1 A0,A4,A0 ; |145| STW .D1T1 A0,*A3 ; |145| || MVKH .S2 0x90080000,B5 ; |152| LDW .D2T2 *B5,B5 ; |152| SHL .S1 A0,24,A0 ; |152| ZERO .D2 B6 ; |152| MVKH .S2 0x90080000,B6 ; |152| NOP 1 CLR .S2 B5,24,27,B5 ; |152| OR .L2X A0,B5,B5 ; |152| STW .D2T2 B5,*B6 ; |152| NOP 9 NOP 3 B .S2 B3 ; |156| MVKL .S2 0x1800004,B5 ; |155| MVKH .S2 0x1800004,B5 ; |155| STW .D2T2 B4,*B5 ; |155| NOP 2 ; BRANCH OCCURS ; |156| .sect ".text:_LED_off" .clink .global _LED_off ;****************************************************************************** ;* FUNCTION NAME: _LED_off * ;* * ;* Regs Modified : A0,A1,A3,A4,A5,A6,A7,B0,B4,B5 * ;* Regs Used : A0,A1,A3,A4,A5,A6,A7,B0,B3,B4,B5 * ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * ;****************************************************************************** _LED_off: ;** --------------------------------------------------------------------------* MVKL .S1 0x1800004,A0 ; |110| MVKH .S1 0x1800004,A0 ; |110| LDW .D1T1 *A0,A7 ; |110| MVKL .S2 0x1800004,B4 ; |114| MVKL .S2 0x1800004,B5 ; |115| MVKH .S2 0x1800004,B4 ; |114| MVKH .S2 0x1800004,B5 ; |115| CLR .S1 A7,4,7,A0 ; |114| SET .S1 A0,5,5,A0 ; |114| STW .D2T1 A0,*B4 ; |114| LDW .D2T2 *B5,B4 ; |115| MVK .S1 240,A0 ; |115| MVK .S1 32,A3 ; |115| MV .D1 A4,A6 ; |108| MVK .S1 0x20,A4 ; |115| AND .S2X A0,B4,B4 ; |115| CMPEQ .L2X B4,A3,B0 ; |115| [ B0] B .S1 L17 ; |115| MVK .S1 0xf0,A5 ; |115| [!B0] MVKL .S1 0x1800004,A3 ; (P) |115| [!B0] MVKH .S1 0x1800004,A3 ; (P) |115| [!B0] LDW .D1T1 *A3,A0 ; (P) ^ |115| NOP 1 ; BRANCH OCCURS ; |115| ;** --------------------------------------------------------------------------* MVK .S2 0x1,B0 NOP 3 AND .S1 A5,A0,A3 ; (P) ^ |115| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 115 ;* Loop opening brace source line : 0 ;* Loop closing brace source line : 0 ;* Known Minimum Trip Count : 1 ;* Known Max Trip Count Factor : 1 ;* Loop Carried Dependency Bound(^) : 8 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 0 ;* .S units 2* 1 ;* .D units 1 0 ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 1 0 ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 1 0 (.L or .S unit) ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 2* 1 ;* Bound(.L .S .D .LS .LSD) 2* 1 ;* ;* Searching for software pipeline schedule at ... ;* ii = 8 Schedule found with 2 iterations in parallel ;* done ;* ;* Loop is interruptible ;* Collapsed epilog stages : 1 ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L14: ; PIPED LOOP PROLOG ;** --------------------------------------------------------------------------* L15: ; PIPED LOOP KERNEL CMPEQ .L1 A3,A4,A1 ; ^ |115| || MVKL .S1 0x1800004,A3 ; @|115| [ A1] ZERO .D2 B0 ; ^ || MVKH .S1 0x1800004,A3 ; @|115| [ B0] B .S2 L15 ; |115| || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |115| NOP 4 AND .S1 A5,A0,A3 ; @ ^ |115| ;** --------------------------------------------------------------------------* L16: ; PIPED LOOP EPILOG ;** --------------------------------------------------------------------------* L17: MVKL .S1 _ledVal,A0 ; |119| MVKH .S1 _ledVal,A0 ; |119| LDW .D1T1 *A0,A0 ; |119| MVKL .S2 _ledVal,B5 ; |119| MVKH .S2 _ledVal,B5 ; |119| ZERO .D2 B4 ; |126| MVKH .S2 0x90080000,B4 ; |126| OR .S1 A0,A6,A0 ; |119| STW .D2T1 A0,*B5 ; |119| LDW .D2T2 *B4,B4 ; |126| SHL .S1 A0,24,A3 ; |126| ZERO .D1 A0 ; |126| MVKH .S1 0x90080000,A0 ; |126| NOP 1 CLR .S2 B4,24,27,B4 ; |126| OR .S2X A3,B4,B4 ; |126| STW .D1T2 B4,*A0 ; |126| NOP 9 NOP 3 B .S2 B3 ; |130| MVKL .S1 0x1800004,A0 ; |129| MVKH .S1 0x1800004,A0 ; |129| STW .D1T1 A7,*A0 ; |129| NOP 2 ; BRANCH OCCURS ; |130| ;****************************************************************************** ;* UNDEFINED EXTERNAL REFERENCES * ;****************************************************************************** .global __BOARD_init