;****************************************************************************** ;* TMS320C6x ANSI C Codegen Version 4.10 Beta (May 4 2001) * ;* Date/Time created: Tue May 29 12:11:56 2001 * ;****************************************************************************** ;****************************************************************************** ;* GLOBAL FILE PARAMETERS * ;* * ;* Architecture : TMS320C671x * ;* Optimization : Enabled at level 3 * ;* Optimizing for : Speed * ;* Based on options: -o3, no -ms * ;* Endian : Little * ;* Interrupt Thrshld : Disabled * ;* Memory Model : Large * ;* Calls to RTS : Far * ;* Pipelining : Enabled * ;* Speculative Load : Disabled * ;* Memory Aliases : Presume are aliases (pessimistic) * ;* Debug Info : No Debug Info * ;* * ;****************************************************************************** .asg A15, FP .asg B14, DP .asg B15, SP .global $bss .sect ".cinit" .align 8 .field 4,32 .field _initialized$1+0,32 .field 0,32 ; _initialized$1 @ 0 .sect ".text" _initialized$1: .usect .far,4,4 ; c:\ti\c6000\cgtools\bin\opt6x.exe -qq -v6711 -O3 C:\WINDOWS\TEMP\TI506495_2 C:\WINDOWS\TEMP\TI506495_4 .sect ".text:__DIP_init" .clink .global __DIP_init ;****************************************************************************** ;* FUNCTION NAME: __DIP_init * ;* * ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,* ;* B5,B6,B7,B8,B9,SP * ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,* ;* B5,B6,B7,B8,B9,SP * ;* Local Frame Size : 0 Args + 0 Auto + 12 Save = 12 byte * ;****************************************************************************** __DIP_init: ;** --------------------------------------------------------------------------* MVKL .S1 _initialized$1,A0 ; |77| MVKH .S1 _initialized$1,A0 ; |77| LDW .D1T1 *A0,A1 ; |77| MVKL .S2 __BOARD_init,B4 ; |78| MVKH .S2 __BOARD_init,B4 ; |78| NOP 2 [ A1] B .S1 L1 ; |77| STW .D2T1 A11,*SP--(16) ; |74| MVKL .S2 RL0,B3 ; |78| || STW .D2T2 B3,*+SP(12) ; |74| || MVK .S1 1,A11 ; |79| MVKL .S1 _initialized$1,A10 ; |79| || STW .D2T1 A10,*+SP(8) ; |74| MVKH .S1 _initialized$1,A10 ; |79| || [ A1] LDW .D2T2 *+SP(12),B3 ; |81| || MVKH .S2 RL0,B3 ; |78| NOP 1 ; BRANCH OCCURS ; |77| ;** --------------------------------------------------------------------------* B .S2 B4 ; |78| NOP 5 RL0: ; CALL OCCURS ; |78| STW .D1T1 A11,*A10 ; |79| LDW .D2T2 *+SP(12),B3 ; |81| NOP 1 ;** --------------------------------------------------------------------------* L1: LDW .D2T1 *+SP(8),A10 ; |81| LDW .D2T1 *++SP(16),A11 ; |81| NOP 1 B .S2 B3 ; |81| NOP 5 ; BRANCH OCCURS ; |81| .sect ".text:_DIP_get" .clink .global _DIP_get ;****************************************************************************** ;* FUNCTION NAME: _DIP_get * ;* * ;* Regs Modified : A0,A1,A3,A4,A5,A6,B0,B4,B5,B6,B7 * ;* Regs Used : A0,A1,A3,A4,A5,A6,B0,B3,B4,B5,B6,B7 * ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * ;****************************************************************************** _DIP_get: ;** --------------------------------------------------------------------------* MVKL .S1 0x1800004,A0 ; |87| MVKH .S1 0x1800004,A0 ; |87| LDW .D1T2 *A0,B4 ; |87| MVKL .S2 0x1800004,B5 ; |92| MVKL .S2 0x1800004,B6 ; |93| MVKH .S2 0x1800004,B5 ; |92| MVKH .S2 0x1800004,B6 ; |93| CLR .S2 B4,4,7,B7 ; |92| SET .S2 B7,5,5,B7 ; |92| STW .D2T2 B7,*B5 ; |92| LDW .D2T2 *B6,B5 ; |93| MVK .S1 240,A3 ; |93| MVK .S1 32,A0 ; |93| MV .L1 A4,A6 ; |85| MVK .S1 0x20,A4 ; |93| AND .L1X A3,B5,A3 ; |93| CMPEQ .L1 A3,A0,A1 ; |93| [ A1] B .S1 L5 ; |93| MVK .S1 0xf0,A5 ; |93| [ A1] ZERO .D1 A0 ; |96| [!A1] MVKL .S1 0x1800004,A3 ; (P) |93| [!A1] MVKH .S1 0x1800004,A3 ; (P) |93| [!A1] LDW .D1T1 *A3,A0 ; (P) ^ |93| ; BRANCH OCCURS ; |93| ;** --------------------------------------------------------------------------* MVK .S2 0x1,B0 NOP 3 AND .S1 A5,A0,A3 ; (P) ^ |93| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 93 ;* Loop opening brace source line : 0 ;* Loop closing brace source line : 0 ;* Known Minimum Trip Count : 1 ;* Known Max Trip Count Factor : 1 ;* Loop Carried Dependency Bound(^) : 8 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 0 ;* .S units 2* 1 ;* .D units 1 0 ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 1 0 ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 1 0 (.L or .S unit) ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 2* 1 ;* Bound(.L .S .D .LS .LSD) 2* 1 ;* ;* Searching for software pipeline schedule at ... ;* ii = 8 Schedule found with 2 iterations in parallel ;* done ;* ;* Loop is interruptible ;* Collapsed epilog stages : 1 ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L2: ; PIPED LOOP PROLOG ;** --------------------------------------------------------------------------* L3: ; PIPED LOOP KERNEL CMPEQ .L1 A3,A4,A1 ; ^ |93| || MVKL .S1 0x1800004,A3 ; @|93| [ A1] ZERO .D2 B0 ; ^ || MVKH .S1 0x1800004,A3 ; @|93| [ B0] B .S2 L3 ; |93| || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |93| NOP 4 AND .S1 A5,A0,A3 ; @ ^ |93| ;** --------------------------------------------------------------------------* L4: ; PIPED LOOP EPILOG ;** --------------------------------------------------------------------------* ZERO .D1 A0 ; |96| ;** --------------------------------------------------------------------------* L5: MVKH .S1 0x90080000,A0 ; |96| LDW .D1T1 *A0,A1 ; |96| MVKL .S2 0x1800004,B5 ; |100| MVKH .S2 0x1800004,B5 ; |100| B .S2 B3 ; |103| STW .D2T2 B4,*B5 ; |100| SHRU .S1 A1,24,A0 ; |97| AND .S1 A6,A0,A1 ; |97| [ A1] MVK .S1 0x1,A1 ; |98| MV .D1 A1,A4 ; |102| ; BRANCH OCCURS ; |103| ;****************************************************************************** ;* UNDEFINED EXTERNAL REFERENCES * ;****************************************************************************** .global __BOARD_init