/* dsk6xinit.gel (version 2.15.05)
 *
 * This GEL file is loaded on the command line of Code Composer.
 * It provides example code for resetting the C6x DSP and initializing
 * the External Memory Interface.
 */

/*
 * The StartUp() function is called every time you start Code Composer.
 * You can customize this function to initialize wait states in the EMIF
 * or to perform other initialization.
 */
StartUp()
{
  setup_memory_map();
  init_emif();
}

menuitem "Resets";

hotmenu Reset_BreakPts_and_EMIF()
{
  GEL_BreakPtReset();
  GEL_Reset();
  init_emif();
}

menuitem "Memory Map";

hotmenu SetMemoryMap()
{
  setup_memory_map();
}

hotmenu ClearMemoryMap()
{
  clear_memory_map();
}

/*
 * Initialize the EMIF
 */
init_emif()
{
  #define EMIF_GCTL         0x01800000
  #define EMIF_CE1          0x01800004
  #define EMIF_CE0          0x01800008
  #define EMIF_CE2          0x01800010
  #define EMIF_CE3          0x01800014
  #define EMIF_SDRAMCTL     0x01800018
  #define EMIF_SDRAMTIMING  0x0180001C
  #define EMIF_SDRAMEXT     0x01800020
  
/*************************************************************************
* Standard 6211/6711 DSK includes 2 MT48LC1M16A1-7 devices = 4MB SDRAM   *
* For these devices use the following parameters:                        *
*   EMIF_SDCTRL=0x07126000                                               *
* If MT48LC1M16A1-10 devices are installed use the following parameters: *
*   EMIF_SDCTRL=0x07227000                                               *
* /|\ 16Mb parts = 4MB SDRAM /|\   *-------------------------------------*
*----------------------------------*   \|/ 64Mb parts = 16MB SDRAM \|/   *
* If MT48LC4M16A2-10 devices are installed use the following parameters: *
*   EMIF_SDCTRL=0x57227000                                               *
*************************************************************************/

  *(int *)EMIF_GCTL = 0x00003040;        /* EMIF global control register         */
  *(int *)EMIF_CE1 = 0xFFFFFF23;         /* CE1 - 32-bit asynch access after boot*/
  *(int *)EMIF_CE0 = 0xFFFFFF30;         /* CE0 - SDRAM                          */
  *(int *)EMIF_CE2 = 0xFFFFFF23;         /* CE2 - 32-bit asynch on daughterboard */
  *(int *)EMIF_CE3 = 0xFFFFFF23;         /* CE3 - 32-bit asynch on daughterboard */
  *(int *)EMIF_SDRAMCTL = 0x07126000;    /* SDRAM control register (100 MHz)*/
  *(int *)EMIF_SDRAMTIMING = 0x0000061A; /* SDRAM Timing register        */
  *(int *)EMIF_SDRAMEXT = 0x00054529;    /* SDRAM Extension register        */
  
}

/*
 * Clear the memory map settings
 */
clear_memory_map()
{
  GEL_MapOff();
}

/*
 * Setup the memory map for the C6211 DSK
 */
setup_memory_map()
{
  /* Enable memory mapping in Code Composer */
  GEL_MapOn();            

  /* Reset all memory to unreadable and unwritable */
  GEL_MapReset();         

  /* Syntax for GEL_MapAdd(address, page, length, readable, writeable)
   *    page:      Program Memory = 0, Data Memory = 1, I/O Space = 2
   *    readable:  Not Readable = 0,  Readable = 1
   *    writeable: Not Writeable = 0, Writeable = 1
   */

/* C6211 DSK-specific memory mapping                                     */
/*-----------------------------------------------------------------------*/
   GEL_MapAdd(0x00000000,0,0x00010000,1,1); /* Internal RAM (L2) mem     */
   GEL_MapAdd(0x01800000,0,0x00000024,1,1); /* EMIF control regs         */
   GEL_MapAdd(0x01840000,0,0x00000004,1,1); /* Cache configuration reg   */
   GEL_MapAdd(0x01844000,0,0x00000020,1,1); /* L2 base addr & count regs */
   GEL_MapAdd(0x01844020,0,0x00000020,1,1); /* L1 base addr & count regs */
   GEL_MapAdd(0x01845000,0,0x00000008,1,1); /* L2 flush & clean regs     */
   GEL_MapAdd(0x01848200,0,0x00000010,1,1); /* CE0 mem attribute regs    */
   GEL_MapAdd(0x01848240,0,0x00000010,1,1); /* CE1 mem attribute regs    */
   GEL_MapAdd(0x01848280,0,0x00000010,1,1); /* CE2 mem attribute regs    */
   GEL_MapAdd(0x018482c0,0,0x00000010,1,1); /* CE3 mem attribute regs    */
   GEL_MapAdd(0x01880000,0,0x00000004,1,1); /* HPI control reg           */
   GEL_MapAdd(0x018c0000,0,0x00000028,1,1); /* McBSP0 regs               */
   GEL_MapAdd(0x01900000,0,0x00000028,1,1); /* McBSP1 regs               */
   GEL_MapAdd(0x01940000,0,0x0000000c,1,1); /* Timer0 regs               */
   GEL_MapAdd(0x01980000,0,0x0000000c,1,1); /* Timer1 regs               */
   GEL_MapAdd(0x019c0000,0,0x0000000c,1,1); /* Interrupt selector regs   */
   GEL_MapAdd(0x01a00000,0,0x00000800,1,1); /* EDMA parameter RAM        */
   GEL_MapAdd(0x01a0ffe0,0,0x00000020,1,1); /* EDMA control regs         */
   GEL_MapAdd(0x02000000,0,0x00000014,0,1); /* QDMA regs                 */
   GEL_MapAdd(0x02000020,0,0x00000014,0,1); /* QDMA pseudo-regs          */
   GEL_MapAdd(0x30000000,0,0x04000000,1,1); /* McBSP0 data               */
   GEL_MapAdd(0x34000000,0,0x04000000,1,1); /* McBSP1 data               */
   GEL_MapAdd(0x80000000,0,0x01000000,1,1); /* CE0, SDRAM, 16 MBytes     */
   GEL_MapAdd(0x90000000,0,0x00020000,1,1); /* CE1, 8-bit ROM, 128 KBytes*/
   GEL_MapAdd(0x90080000,0,0x00000004,1,1); /* CE1, 8-bit I/O port       */
   GEL_MapAdd(0xA0000000,0,0x10000000,1,1); /* CE2 - Daughtercard        */
   GEL_MapAdd(0xB0000000,0,0x10000000,1,1); /* CE3 - Daughtercard        */
}