;******************************************************************************
;* TMS320C6x C/C++ Codegen                                    PC Version 4.36 *
;* Date/Time created: Thu Mar 18 16:06:11 2004                                *
;******************************************************************************

;******************************************************************************
;* GLOBAL FILE PARAMETERS                                                     *
;*                                                                            *
;*   Architecture      : TMS320C670x                                          *
;*   Optimization      : Enabled at level 3                                   *
;*   Optimizing for    : Speed                                                *
;*                       Based on options: -o3, no -ms                        *
;*   Endian            : Little                                               *
;*   Interrupt Thrshld : Disabled                                             *
;*   Memory Model      : Small                                                *
;*   Calls to RTS      : Near                                                 *
;*   Pipelining        : Enabled                                              *
;*   Speculative Load  : Disabled                                             *
;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
;*   Debug Info        : No Debug Info                                        *
;*                                                                            *
;******************************************************************************

	.asg	A15, FP
	.asg	B14, DP
	.asg	B15, SP
	.global	$bss


	.sect	".cinit"
	.align	8
	.field  	IR_1,32
	.field  	_coeff+0,32
	.word	03bff9724h		; _coeff[0] @ 0
	.word	03c4154cah		; _coeff[1] @ 32
	.word	03cbb98c8h		; _coeff[2] @ 64
	.word	03d23d70ah		; _coeff[3] @ 96
	.word	03d79db23h		; _coeff[4] @ 128
	.word	03da8f5c3h		; _coeff[5] @ 160
	.word	03dcf0d84h		; _coeff[6] @ 192
	.word	03de90ff9h		; _coeff[7] @ 224
	.word	03df212d7h		; _coeff[8] @ 256
	.word	03de90ff9h		; _coeff[9] @ 288
	.word	03dcf0d84h		; _coeff[10] @ 320
	.word	03da8f5c3h		; _coeff[11] @ 352
	.word	03d79db23h		; _coeff[12] @ 384
	.word	03d23d70ah		; _coeff[13] @ 416
	.word	03cbb98c8h		; _coeff[14] @ 448
	.word	03c4154cah		; _coeff[15] @ 480
	.word	03bff9724h		; _coeff[16] @ 512
IR_1:	.set	68

	.sect	".text"
	.global	_coeff
	.bss	_coeff,68,4
	.global	_buffer
_buffer:	.usect	"SDRAM",24576,4

	.sect	".cinit:c"
	.align	8
	.field  	(CIR - $) - 8, 32
	.field  	_buffer_ready+0,32
	.field  	0,16			; _buffer_ready @ 0

	.sect	".text"
	.global	_buffer_ready
_buffer_ready:	.usect	".bss:c",2,2

	.sect	".cinit:c"
	.align	2
	.field  	0,16			; _over_run @ 0

	.sect	".text"
	.global	_over_run
_over_run:	.usect	".bss:c",2,2

	.sect	".cinit:c"
	.align	2
	.field  	0,16			; _ready_index @ 0

	.sect	".text"
	.global	_ready_index
_ready_index:	.usect	".bss:c",2,2
	.global	_sineObjL
	.bss	_sineObjL,56,4
	.global	_sineObjR
	.bss	_sineObjR,56,4
	.global	_rDelayBuff
	.bss	_rDelayBuff,4096,4
	.bss	_Left$1,8192,4
	.bss	_Right$2,8192,4

	.sect	".cinit:c"
	.align	4
	.word	03f800000h		; _lVol$3 @ 0

	.sect	".text"
_lVol$3:	.usect	".bss:c",4,4

	.sect	".cinit:c"
	.align	4
	.word	03f800000h		; _rVol$4 @ 0

	.sect	".text"
_rVol$4:	.usect	".bss:c",4,4
;	c:\ti\c6000\cgtools\bin\opt6x.exe -v6700 -q -O3 C:\DOCUME~1\yoder\LOCALS~1\Temp\TI2436_2 C:\DOCUME~1\yoder\LOCALS~1\Temp\TI2436_5 -w C:/Documents and Settings/yoder/My Documents/Classes/ece581/My Labs/solutions/lab02/Frame_EDMA\\Release 

	.sect	".text"
	.global	_ZeroBuffers

;******************************************************************************
;* FUNCTION NAME: _ZeroBuffers                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
;*                           B6,B7,B8,B9,B13,SP                               *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
;*                           B6,B7,B8,B9,B13,DP,SP                            *
;*   Local Frame Size  : 0 Args + 0 Auto + 8 Save = 8 byte                    *
;******************************************************************************
_ZeroBuffers:
;** --------------------------------------------------------------------------*
           MVKL    .S1     _buffer-4,A0      ; |54| 
           MVKH    .S1     _buffer-4,A0      ; |54| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 56
;*      Loop opening brace source line   : 57
;*      Loop closing brace source line   : 57
;*      Loop Unroll Multiple             : 2x
;*      Known Minimum Trip Count         : 6144
;*      Known Maximum Trip Count         : 6144
;*      Known Max Trip Count Factor      : 6144
;*      Loop Carried Dependency Bound(^) : 0
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1*       0     
;*      .D units                     1*       1*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1*       1*    
;*      Long read paths              1*       1*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1*       0     
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 1  Schedule found with 7 iterations in parallel
;*      Done
;*
;*      Epilog not entirely removed
;*      Collapsed epilog stages     : 3
;*      Collapsed prolog stages     : 0
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 4 (after unrolling)
;*----------------------------------------------------------------------------*
L1:    ; PIPED LOOP PROLOG
           B       .S1     L2                ; |57| (P) <0,1> 
           B       .S1     L2                ; |57| (P) <1,1> 

           MVK     .S2     0x1800,B4         ; |56| 
||         B       .S1     L2                ; |57| (P) <2,1> 

           ZERO    .S2     B5
||         STW     .D2T1   A10,*SP--(8)      ; |52| 
||         SUB     .L2     B4,9,B0
||         B       .S1     L2                ; |57| (P) <3,1> 

           ZERO    .D1     A3
||         STW     .D2T2   B13,*+SP(4)       ; |52| 
||         MV      .L2     B3,B13            ; |52| 
||         ADD     .S2X    2,A0,B4
||         B       .S1     L2                ; |57| (P) <4,1> 

;** --------------------------------------------------------------------------*
L2:    ; PIPED LOOP KERNEL

           STH     .D1T1   A3,*++A0(4)       ; |57| <0,6> 
||         STH     .D2T2   B5,*++B4(4)       ; |57| <0,6> 
|| [ B0]   B       .S1     L2                ; |57| <5,1> 
|| [ B0]   SUB     .S2     B0,1,B0           ; |57| <6,0> 

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 59
;*      Loop opening brace source line   : 59
;*      Loop closing brace source line   : 61
;*      Loop Unroll Multiple             : 2x
;*      Known Minimum Trip Count         : 512
;*      Known Maximum Trip Count         : 512
;*      Known Max Trip Count Factor      : 512
;*      Loop Carried Dependency Bound(^) : 0
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1*       0     
;*      .D units                     1*       1*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1*       1*    
;*      Long read paths              1*       1*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1*       0     
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 1  Schedule found with 7 iterations in parallel
;*      Done
;*
;*      Epilog not entirely removed
;*      Collapsed epilog stages     : 1
;*      Collapsed prolog stages     : 0
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 6 (after unrolling)
;*----------------------------------------------------------------------------*
L3:    ; PIPED LOOP EPILOG AND PROLOG

           MVK     .S2     (_rDelayBuff-8-$bss),B6
||         STH     .D1T1   A3,*++A0(4)       ; |57| (E) <4,6> 
||         STH     .D2T2   B5,*++B4(4)       ; |57| (E) <4,6> 
||         B       .S1     L4                ; |61| (P) <0,1> 

           MVK     .S2     0x200,B6          ; |59| 
||         ADD     .L2     DP,B6,B7
||         STH     .D2T2   B5,*++B4(4)       ; |57| (E) <5,6> 
||         STH     .D1T1   A3,*++A0(4)       ; |57| (E) <5,6> 
||         B       .S1     L4                ; |61| (P) <1,1> 

           SUB     .S2     B6,11,B0
||         ZERO    .L2     B5
||         ZERO    .L1     A3
||         STH     .D1T1   A3,*++A0(4)       ; |57| (E) <6,6> 
||         STH     .D2T2   B5,*++B4(4)       ; |57| (E) <6,6> 
||         B       .S1     L4                ; |61| (P) <2,1> 

           ADD     .D2     4,B7,B4
||         MV      .L1X    B7,A0
||         B       .S1     L4                ; |61| (P) <3,1> 

           B       .S1     L4                ; |61| (P) <4,1> 
;** --------------------------------------------------------------------------*
L4:    ; PIPED LOOP KERNEL

           STW     .D1T1   A3,*++A0(8)       ; |60| <0,6> 
||         STW     .D2T2   B5,*++B4(8)       ; |60| <0,6> 
|| [ B0]   B       .S1     L4                ; |61| <5,1> 
|| [ B0]   SUB     .S2     B0,1,B0           ; |61| <6,0> 

;** --------------------------------------------------------------------------*
L5:    ; PIPED LOOP EPILOG

           MVKL    .S2     RL0,B3            ; |63| 
||         MVKL    .S1     0x472c4400,A10    ; |63| 
||         STW     .D2T2   B5,*++B4(8)       ; |60| (E) <2,6> 
||         STW     .D1T1   A3,*++A0(8)       ; |60| (E) <2,6> 

           MVKH    .S1     0x472c4400,A10    ; |63| 
||         CALL    .S2     _SINE_init        ; |63| 
||         STW     .D2T2   B5,*++B4(8)       ; |60| (E) <3,6> 
||         STW     .D1T1   A3,*++A0(8)       ; |60| (E) <3,6> 

           MVKH    .S2     RL0,B3            ; |63| 
||         MV      .S1     A10,A6            ; |63| 
||         STW     .D1T1   A3,*++A0(8)       ; |60| (E) <4,6> 
||         STW     .D2T2   B5,*++B4(8)       ; |60| (E) <4,6> 

           STW     .D2T2   B5,*++B4(8)       ; |60| (E) <5,6> 
||         STW     .D1T1   A3,*++A0(8)       ; |60| (E) <5,6> 

           STW     .D1T1   A3,*++A0(8)       ; |60| (E) <6,6> 
||         STW     .D2T2   B5,*++B4(8)       ; |60| (E) <6,6> 

           ZERO    .D2     B4                ; |63| 
||         MVK     .S1     (_sineObjL-$bss),A0 ; |63| 

           ADD     .S1X    DP,A0,A4          ; |63| 
||         MVKH    .S2     0x43dc0000,B4     ; |63| 

RL0:       ; CALL OCCURS                     ; |63| 
           CALL    .S2     _SINE_init        ; |64| 

           MV      .D1     A10,A6            ; |63| 
||         ZERO    .D2     B4                ; |64| 
||         MVK     .S1     (_sineObjR-$bss),A0 ; |64| 
||         MVKL    .S2     RL1,B3            ; |64| 

           ADD     .S1X    DP,A0,A4          ; |64| 
||         MVKH    .S2     0x445c0000,B4     ; |64| 

           MVKH    .S2     RL1,B3            ; |64| 
           NOP             2
RL1:       ; CALL OCCURS                     ; |64| 
           NOP             1

           LDW     .D2T2   *+SP(4),B13       ; |65| 
||         MV      .S2     B13,B3            ; |65| 

           RET     .S2     B3                ; |65| 
||         LDW     .D2T1   *++SP(8),A10      ; |65| 

           NOP             5
           ; BRANCH OCCURS                   ; |65| 



	.sect	".text"
	.global	_ProcessBuffer

;******************************************************************************
;* FUNCTION NAME: _ProcessBuffer                                              *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;*                           B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,SP    *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,B0,*
;*                           B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,DP,SP *
;*   Local Frame Size  : 8 Args + 0 Auto + 36 Save = 44 byte                  *
;******************************************************************************
_ProcessBuffer:
;** --------------------------------------------------------------------------*
           LDH     .D2T2   *+DP(_ready_index),B4 ; |82| 

           MV      .S1X    SP,A9             ; |81| 
||         STW     .D2T1   A14,*SP--(48)     ; |81| 

           STW     .D2T2   B13,*+SP(44)
           STW     .D2T2   B12,*+SP(40)

           MVKL    .S1     _buffer,A0        ; |82| 
||         STW     .D1T1   A12,*-A9(24)
||         MVC     .S2     CSR,B7
||         STW     .D2T2   B11,*+SP(36)

           MVKH    .S1     _buffer,A0        ; |82| 
||         STW     .D1T1   A13,*-A9(20)
||         AND     .L2     -2,B7,B6
||         STW     .D2T2   B10,*+SP(32)
||         SHL     .S2     B4,13,B4          ; |82| 

           MVC     .S2     B6,CSR            ; interrupts off
||         MVK     .S1     0x800,A0          ; |98| 
||         STW     .D2T1   A11,*+SP(20)
||         ADD     .L1X    A0,B4,A3          ; |82| 

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 98
;*      Loop opening brace source line   : 98
;*      Loop closing brace source line   : 101
;*      Known Minimum Trip Count         : 2048
;*      Known Maximum Trip Count         : 2048
;*      Known Max Trip Count Factor      : 2048
;*      Loop Carried Dependency Bound(^) : 0
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        2*    
;*      .S units                     1        0     
;*      .D units                     2*       2*    
;*      .M units                     0        0     
;*      .X cross paths               0        2*    
;*      .T address paths             2*       2*    
;*      Long read paths              0        2*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        1     
;*      Bound(.L .S .D .LS .LSD)     2*       2*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 2  Schedule found with 6 iterations in parallel
;*      Done
;*
;*      Epilog not removed
;*      Collapsed epilog stages     : 0
;*
;*      Prolog not entirely removed
;*      Collapsed prolog stages     : 3
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      For further improvement on this loop, try option -mh4
;*
;*      Minimum safe trip count     : 5
;*----------------------------------------------------------------------------*
L6:    ; PIPED LOOP PROLOG

           SUB     .D1     A3,4,A3
||         B       .S1     L7                ; |101| (P) <0,5> 
||         STW     .D2T1   A10,*+SP(16)

           MVK     .S2     (_Left$1-$bss),B5 ; |84| 
||         SUB     .S1     A0,5,A1
||         LDH     .D1T1   *++A3(4),A0       ; |99| (P) <0,0> 

           MVK     .S2     (_Right$2-$bss),B4 ; |84| 
||         LDH     .D1T1   *+A3(2),A0        ; |100| (P) <0,1> 
||         B       .S1     L7                ; |101| (P) <1,5> 

           MVK     .S1     0x3,A2            ; init prolog collapse predicate
||         ADD     .D2     DP,B4,B5          ; |84| 
||         ADD     .S2     DP,B5,B4          ; |84| 
||         MV      .L2     B3,B13
||         LDH     .D1T1   *++A3(4),A0       ; |99| (P) <1,0> 

;** --------------------------------------------------------------------------*
L7:    ; PIPED LOOP KERNEL

   [!A2]   STW     .D2T2   B6,*B5++          ; |99| <0,9> 
||         INTSP   .L2X    A0,B6             ; |99| <2,5> 
|| [ A1]   B       .S1     L7                ; |101| <2,5> 
||         LDH     .D1T1   *+A3(2),A0        ; |100| <4,1> 

   [ A2]   SUB     .S1     A2,1,A2           ; <0,10> 
|| [!A2]   STW     .D2T2   B6,*B4++          ; |100| <0,10> 
||         INTSP   .L2X    A0,B6             ; |100| <2,6> 
|| [ A1]   SUB     .L1     A1,1,A1           ; |101| <3,4> 
||         LDH     .D1T1   *++A3(4),A0       ; |99| <5,0> 

;** --------------------------------------------------------------------------*
L8:    ; PIPED LOOP EPILOG

           MVK     .S1     0x4,A4            ; |106| 
||         MVKL    .S2     RL2,B3            ; |106| 
||         INTSP   .L2X    A0,B6             ; |99| (E) <3,5> 
||         LDH     .D1T1   *+A3(2),A0        ; |100| (E) <5,1> 
||         STW     .D2T2   B6,*B5++          ; |99| (E) <1,9> 

           MVKH    .S2     RL2,B3            ; |106| 
||         STW     .D2T2   B6,*B4++          ; |100| (E) <1,10> 
||         INTSP   .L2X    A0,B6             ; |100| (E) <3,6> 

           INTSP   .L2X    A0,B6             ; |99| (E) <4,5> 
||         STW     .D2T2   B6,*B5++          ; |99| (E) <2,9> 

           STW     .D2T2   B6,*B4++          ; |100| (E) <2,10> 
||         INTSP   .L2X    A0,B6             ; |100| (E) <4,6> 

           INTSP   .L2X    A0,B6             ; |99| (E) <5,5> 
||         STW     .D2T2   B6,*B5++          ; |99| (E) <3,9> 

           MVK     .S1     (_Right$2-$bss),A0 ; |84| 
||         STW     .D2T2   B6,*B4++          ; |100| (E) <3,10> 
||         INTSP   .L2X    A0,B6             ; |100| (E) <5,6> 

           ADD     .S1X    DP,A0,A12         ; |84| 
||         STW     .D2T2   B6,*B5++          ; |99| (E) <4,9> 

           STW     .D2T2   B6,*B4++          ; |100| (E) <4,10> 

           MVC     .S2     B7,CSR            ; interrupts on
||         STW     .D2T2   B6,*B5++          ; |99| (E) <5,9> 

;** --------------------------------------------------------------------------*

           MVK     .S2     (_Left$1-$bss),B5 ; |84| 
||         STW     .D2T2   B6,*B4++          ; |100| (E) <5,10> 

           ADD     .D2     DP,B5,B11         ; |84| 
||         MVKL    .S2     _DIP_get,B4       ; |106| 

           MVKH    .S2     _DIP_get,B4       ; |106| 
           CALL    .S2     B4                ; |106| 
           NOP             5
RL2:       ; CALL OCCURS                     ; |106| 

           MV      .L1X    B11,A4            ; |107| 
||         MV      .D1     A4,A1             ; |106| 
||         MVKL    .S2     RL3,B3            ; |107| 
||         MVK     .S1     (_coeff-$bss),A0  ; |107| 
||         MV      .L2X    A12,B4            ; |107| 

   [ A1]   B       .S2     L9                ; |106| 
||         ADD     .L1X    DP,A0,A6          ; |107| 
||         MVK     .S1     0x11,A8           ; |107| 

           MVKH    .S2     RL3,B3            ; |107| 
           MVK     .S2     0x800,B6          ; |107| 
   [ A1]   MVKL    .S2     _DIP_get,B4       ; |110| 
   [ A1]   MVKH    .S2     _DIP_get,B4       ; |110| 
           NOP             1
           ; BRANCH OCCURS                   ; |106| 
;** --------------------------------------------------------------------------*
           CALL    .S1     _FIRfilter        ; |107| 
           NOP             5
RL3:       ; CALL OCCURS                     ; |107| 
           MVKL    .S2     _DIP_get,B4       ; |110| 
           MVKH    .S2     _DIP_get,B4       ; |110| 
;** --------------------------------------------------------------------------*
L9:    
           CALL    .S2     B4                ; |110| 
           MVKL    .S2     RL4,B3            ; |110| 
           MVKH    .S2     RL4,B3            ; |110| 
           MVK     .S1     0x1,A4            ; |110| 
           NOP             2
RL4:       ; CALL OCCURS                     ; |110| 
           MVKL    .S2     SL1+0,B6          ; |111| 
           MVKL    .S2     SL2+0,B7          ; |119| 

           MVKL    .S1     _logTrace,A0      ; |111| 
||         MV      .D1     A4,A1             ; |110| 
||         MVK     .S2     0x800,B5          ; |112| 

           MVKL    .S2     _buffer,B4        ; |82| 
|| [ A1]   B       .S1     L11               ; |110| 

           MVKL    .S1     _logTrace,A3      ; |119| 
||         MVKH    .S2     _buffer,B4        ; |82| 

           MVK     .S1     (_sineObjR-$bss),A13
||         MVKH    .S2     SL1+0,B6          ; |111| 

           MVK     .S1     (_sineObjL-$bss),A14
||         MVKH    .S2     SL2+0,B7          ; |119| 

           MVKH    .S1     _logTrace,A0      ; |111| 
||         MVKL    .S2     RL5,B3            ; |111| 
||         MV      .L1X    B11,A10           ; |103| 

           MVKH    .S1     _logTrace,A3      ; |119| 
||         MV      .L2X    A12,B10           ; |104| 
||         MVKH    .S2     RL5,B3            ; |111| 
||         MV      .L1X    B5,A11            ; |112| 
||         MV      .D2     B4,B12            ; |82| 
||         MV      .D1     A0,A4             ; |111| 

           ; BRANCH OCCURS                   ; |110| 
;** --------------------------------------------------------------------------*
           CALL    .S1     _LOG_printf       ; |111| 
           STW     .D2T2   B6,*+SP(4)        ; |111| 
           NOP             4
RL5:       ; CALL OCCURS                     ; |111| 
           ADD     .S1X    DP,A13,A13
           ADD     .S1X    DP,A14,A14
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*      Disqualified loop: Loop contains a call
;*----------------------------------------------------------------------------*
L10:    
           CALL    .S1     _sineGen          ; |113| 
           MVKL    .S2     RL6,B3            ; |113| 
           MVKH    .S2     RL6,B3            ; |113| 
           MV      .D1     A14,A4            ; |113| 
           NOP             2
RL6:       ; CALL OCCURS                     ; |113| 
           LDW     .D2T1   *+DP(_lVol$3),A0  ; |113| 
           INTSP   .L2X    A4,B4             ; |113| 
           LDW     .D1T1   *A10,A3           ; |113| 
           MVKL    .S2     RL7,B3            ; |115| 
           MVKH    .S2     RL7,B3            ; |115| 
           MPYSP   .M1X    A0,B4,A0          ; |113| 
           MV      .S1     A13,A4            ; |115| 
           NOP             1
           CALL    .S1     _sineGen          ; |115| 
           ADDSP   .L1     A0,A3,A0          ; |113| 
           NOP             3
           STW     .D1T1   A0,*A10++         ; |113| 
RL7:       ; CALL OCCURS                     ; |115| 
           LDW     .D2T2   *+DP(_rVol$4),B5  ; |115| 
           INTSP   .L1     A4,A0             ; |115| 
           LDW     .D2T2   *B10,B4           ; |115| 
           SUB     .D1     A11,1,A1          ; |117| 
           SUB     .D1     A11,1,A11         ; |117| 
           MPYSP   .M2X    B5,A0,B5          ; |115| 
           NOP             2
   [ A1]   B       .S1     L10               ; |117| 
           ADDSP   .L2     B5,B4,B4          ; |115| 
           NOP             3
           STW     .D2T2   B4,*B10++         ; |115| 
           ; BRANCH OCCURS                   ; |117| 
;** --------------------------------------------------------------------------*
           B       .S1     L12               ; |117| 
           NOP             5
           ; BRANCH OCCURS                   ; |117| 
;** --------------------------------------------------------------------------*
L11:    
           CALL    .S1     _LOG_printf       ; |119| 
           STW     .D2T2   B7,*+SP(4)        ; |119| 
           MV      .D1     A3,A4             ; |119| 
           NOP             1
           MVKL    .S2     RL8,B3            ; |119| 
           MVKH    .S2     RL8,B3            ; |119| 
RL8:       ; CALL OCCURS                     ; |119| 
;** --------------------------------------------------------------------------*
L12:    
           LDH     .D2T2   *+DP(_ready_index),B4 ; |122| 
           NOP             1
           MVC     .S2     CSR,B9
           AND     .S2     -2,B9,B6
           MVC     .S2     B6,CSR            ; interrupts off
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 132
;*      Loop opening brace source line   : 132
;*      Loop closing brace source line   : 135
;*      Known Minimum Trip Count         : 2048
;*      Known Maximum Trip Count         : 2048
;*      Known Max Trip Count Factor      : 2048
;*      Loop Carried Dependency Bound(^) : 0
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     1        1     
;*      .S units                     2*       1     
;*      .D units                     2*       2*    
;*      .M units                     1        1     
;*      .X cross paths               0        1     
;*      .T address paths             2*       2*    
;*      Long read paths              1        1     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             2*       1     
;*      Bound(.L .S .D .LS .LSD)     2*       2*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 2  Schedule found with 9 iterations in parallel
;*      Done
;*
;*      Epilog not removed
;*      Collapsed epilog stages     : 0
;*
;*      Prolog not entirely removed
;*      Collapsed prolog stages     : 6
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      For further improvement on this loop, try option -mh20
;*
;*      Minimum safe trip count     : 8
;*----------------------------------------------------------------------------*
L13:    ; PIPED LOOP PROLOG

           MV      .D2     B11,B4            ; |123| 
||         B       .S1     L14               ; |135| (P) <0,11> 
||         SHL     .S2     B4,13,B5          ; |122| 

           MVK     .S1     0x800,A1          ; init prolog collapse predicate
||         MV      .D1     A12,A3            ; |124| 
||         LDW     .D2T2   *B4++,B6          ; |134| (P) <0,0> 
||         ADD     .S2     B12,B5,B6         ; |122| 

           ZERO    .L1     A0
||         MVK     .S2     0x800,B7          ; |132| 
||         B       .S1     L14               ; |135| (P) <1,11> 
||         LDW     .D1T1   *A3++,A8          ; |133| (P) <0,1> 
||         SUB     .D2     B6,4,B5

           SUB     .S2     B7,5,B0
||         MVKH    .S1     0x47800000,A0
||         LDW     .D2T2   *B4++,B6          ; |134| (P) <1,0> 
||         SUB     .L1X    B6,4,A5
||         ADD     .L2     2,B5,B5

;** --------------------------------------------------------------------------*
L14:    ; PIPED LOOP KERNEL

   [ A1]   MPYSU   .M1     2,A1,A1           ; <0,15> 
|| [!A1]   STH     .D2T2   B7,*++B5(4)       ; |134| <0,15> 
|| [ B0]   B       .S1     L14               ; |135| <2,11> 
|| [ B0]   SUB     .S2     B0,1,B0           ; |135| <3,9> 
||         LDW     .D1T1   *A3++,A8          ; |133| <7,1> 

   [!A1]   STH     .D1T1   A6,*++A5(4)       ; |133| <0,16> 
||         SHR     .S1     A7,16,A6          ; |133| <1,14> 
||         SHR     .S2     B8,16,B7          ; |134| <1,14> 
||         SPINT   .L1     A4,A7             ; |133| <3,10> 
||         SPINT   .L2     B7,B8             ; |134| <3,10> 
||         MPYSP   .M1     A0,A8,A4          ; |133| <5,6> 
||         MPYSP   .M2X    A0,B6,B7          ; |134| <5,6> 
||         LDW     .D2T2   *B4++,B6          ; |134| <8,0> 

;** --------------------------------------------------------------------------*
L15:    ; PIPED LOOP EPILOG

           MV      .S1X    SP,A9             ; |168| 
||         MV      .S2     B13,B3            ; |168| 
||         LDW     .D1T1   *A3++,A8          ; |133| (E) <8,1> 
||         STH     .D2T2   B7,*++B5(4)       ; |134| (E) <1,15> 

           ZERO    .D2     B4                ; |153| 
||         STH     .D1T1   A6,*++A5(4)       ; |133| (E) <1,16> 
||         SHR     .S2     B8,16,B7          ; |134| (E) <2,14> 
||         SPINT   .L1     A4,A4             ; |133| (E) <4,10> 
||         SPINT   .L2     B7,B8             ; |134| (E) <4,10> 
||         MPYSP   .M1     A0,A8,A3          ; |133| (E) <6,6> 
||         MPYSP   .M2X    A0,B6,B7          ; |134| (E) <6,6> 
||         SHR     .S1     A7,16,A3          ; |133| (E) <2,14> 

           STH     .D2T2   B7,*++B5(4)       ; |134| (E) <2,15> 

           STH     .D1T1   A3,*++A5(4)       ; |133| (E) <2,16> 
||         SHR     .S2     B8,16,B7          ; |134| (E) <3,14> 
||         SPINT   .L1     A4,A4             ; |133| (E) <5,10> 
||         SPINT   .L2     B7,B7             ; |134| (E) <5,10> 
||         MPYSP   .M1     A0,A8,A3          ; |133| (E) <7,6> 
||         MPYSP   .M2X    A0,B6,B6          ; |134| (E) <7,6> 
||         SHR     .S1     A7,16,A6          ; |133| (E) <3,14> 

           STH     .D2T2   B7,*++B5(4)       ; |134| (E) <3,15> 

           STH     .D1T1   A6,*++A5(4)       ; |133| (E) <3,16> 
||         SHR     .S2     B8,16,B6          ; |134| (E) <4,14> 
||         SPINT   .L1     A3,A4             ; |133| (E) <6,10> 
||         SPINT   .L2     B7,B7             ; |134| (E) <6,10> 
||         MPYSP   .M1     A0,A8,A3          ; |133| (E) <8,6> 
||         MPYSP   .M2X    A0,B6,B6          ; |134| (E) <8,6> 
||         SHR     .S1     A4,16,A0          ; |133| (E) <4,14> 

           STH     .D2T2   B6,*++B5(4)       ; |134| (E) <4,15> 

           STH     .D1T1   A0,*++A5(4)       ; |133| (E) <4,16> 
||         SHR     .S2     B7,16,B6          ; |134| (E) <5,14> 
||         SPINT   .L1     A3,A0             ; |133| (E) <7,10> 
||         SPINT   .L2     B6,B6             ; |134| (E) <7,10> 
||         SHR     .S1     A4,16,A0          ; |133| (E) <5,14> 

           STH     .D2T2   B6,*++B5(4)       ; |134| (E) <5,15> 

           STH     .D1T1   A0,*++A5(4)       ; |133| (E) <5,16> 
||         SHR     .S2     B7,16,B6          ; |134| (E) <6,14> 
||         SPINT   .L1     A3,A0             ; |133| (E) <8,10> 
||         SPINT   .L2     B6,B6             ; |134| (E) <8,10> 
||         SHR     .S1     A4,16,A3          ; |133| (E) <6,14> 

           STH     .D2T2   B6,*++B5(4)       ; |134| (E) <6,15> 

           STH     .D1T1   A3,*++A5(4)       ; |133| (E) <6,16> 
||         SHR     .S2     B6,16,B6          ; |134| (E) <7,14> 
||         SHR     .S1     A0,16,A3          ; |133| (E) <7,14> 

           MVC     .S2     B9,CSR            ; interrupts on
||         STH     .D2T2   B6,*++B5(4)       ; |134| (E) <7,15> 

           SHR     .S1     A0,16,A0          ; |133| (E) <8,14> 
||         STH     .D1T1   A3,*++A5(4)       ; |133| (E) <7,16> 
||         SHR     .S2     B6,16,B6          ; |134| (E) <8,14> 

           STH     .D2T2   B6,*++B5(4)       ; |134| (E) <8,15> 
           STH     .D1T1   A0,*++A5(4)       ; |133| (E) <8,16> 

           LDH     .D2T2   *+DP(_ready_index),B5 ; |152| 
||         LDDW    .D1T1   *+A9(24),A13:A12  ; |168| 

           LDDW    .D2T2   *+SP(32),B11:B10  ; |168| 
||         LDDW    .D1T1   *+A9(16),A11:A10  ; |168| 

           RET     .S2     B3                ; |168| 
||         LDDW    .D2T2   *+SP(40),B13:B12  ; |168| 

           LDW     .D2T1   *++SP(48),A14     ; |168| 
           STH     .D2T2   B4,*+DP(_buffer_ready) ; |153| 
           NOP             3
           ; BRANCH OCCURS                   ; |168| 



	.sect	".text"
	.global	_IsOverRun

;******************************************************************************
;* FUNCTION NAME: _IsOverRun                                                  *
;*                                                                            *
;*   Regs Modified     : A4                                                   *
;*   Regs Used         : A4,B3,DP                                             *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_IsOverRun:
;** --------------------------------------------------------------------------*
           RET     .S2     B3                ; |200| 
           LDH     .D2T1   *+DP(_over_run),A4 ; |199| 
           NOP             4
           ; BRANCH OCCURS                   ; |200| 



	.sect	".text"
	.global	_IsBufferReady

;******************************************************************************
;* FUNCTION NAME: _IsBufferReady                                              *
;*                                                                            *
;*   Regs Modified     : A4                                                   *
;*   Regs Used         : A4,B3,DP                                             *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_IsBufferReady:
;** --------------------------------------------------------------------------*
           RET     .S2     B3                ; |184| 
           LDH     .D2T1   *+DP(_buffer_ready),A4 ; |183| 
           NOP             4
           ; BRANCH OCCURS                   ; |184| 



	.sect	".text"
	.global	_EDMA_ISR

;******************************************************************************
;* FUNCTION NAME: _EDMA_ISR                                                   *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6,  *
;*                           B7,B8,B9,SP                                      *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6,  *
;*                           B7,B8,B9,DP,SP                                   *
;*   Local Frame Size  : 0 Args + 0 Auto + 4 Save = 4 byte                    *
;******************************************************************************
_EDMA_ISR:
;** --------------------------------------------------------------------------*
           MVKL    .S1     _LED_toggle,A0    ; |216| 
           MVKH    .S1     _LED_toggle,A0    ; |216| 
           CALL    .S2X    A0                ; |216| 
           STW     .D2T2   B3,*SP--(8)       ; |215| 
           MVKL    .S2     RL9,B3            ; |216| 
           MVKH    .S2     RL9,B3            ; |216| 
           MVK     .S1     0x1,A4            ; |216| 
           NOP             1
RL9:       ; CALL OCCURS                     ; |216| 

           MVKL    .S2     0x8000,B4         ; |581| 
||         MVKL    .S1     0x1a0ffe4,A0      ; |581| 

           MVKH    .S2     0x8000,B4         ; |581| 
||         MVKH    .S1     0x1a0ffe4,A0      ; |581| 

           STW     .D1T2   B4,*A0            ; |581| 
           LDH     .D2T2   *+DP(_ready_index),B4 ; |220| 
           MVK     .S1     1,A0              ; |224| 
           NOP             3
           ADD     .D2     1,B4,B4           ; |220| 
           EXT     .S2     B4,16,16,B5       ; |220| 

           ZERO    .S2     B4                ; |221| 
||         STH     .D2T2   B4,*+DP(_ready_index) ; |220| 
||         CMPLT   .L2     B5,3,B0           ; |220| 

   [!B0]   STH     .D2T2   B4,*+DP(_ready_index) ; |221| 
           LDH     .D2T2   *+DP(_buffer_ready),B6 ; |222| 
           LDW     .D2T2   *++SP(8),B3       ; |227| 
           CALLRET .S1     _SWI_post         ; |226| 
           MVK     .S2     1,B5              ; |223| 
           MVKL    .S2     _processBufferSwi,B4 ; |226| 
           CMPEQ   .L2     B6,1,B0           ; |222| 

   [ B0]   STH     .D2T2   B5,*+DP(_over_run) ; |223| 
||         MVKH    .S2     _processBufferSwi,B4 ; |226| 

           STH     .D2T1   A0,*+DP(_buffer_ready) ; |224| 
||         MV      .S1X    B4,A4             ; |226| 

RL10:      ; CALL OCCURS                     ; |227| ; bypass _EDMA_ISR upon return


;******************************************************************************
;* MARK THE END OF THE SCALAR INIT RECORD IN CINIT:C                          *
;******************************************************************************

CIR:	.sect	".cinit:c"
;******************************************************************************
;* STRINGS                                                                    *
;******************************************************************************
	.sect	".const"
SL1:	.string	"Add Sine ENabled",0
SL2:	.string	"Add Sine DISabled",0
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES                                              *
;******************************************************************************
	.global	_DIP_get
	.global	_LED_toggle
	.global	_SWI_post
	.global	_LOG_printf
	.global	_SINE_init
	.global	_sineGen
	.global	_FIRfilter
	.global	_processBufferSwi
	.global	_logTrace