///////////////////////////////////////////////////////////////////////
// Filename: DSK_Support.c
//
// Synopsis: Functions to support basic initialization of the DSK
//           hardware resources using DSP/BIOS.
//           Support is provided for the 6711 and 6713 DSKs
//
// Authors:  Michael G. Morrow, 3/17/2004
//
// Changes by:  Mark A. Yoder
//
// Date of Last Revision: 25-Mar-2004
//
// Copyright (c): 2001-2004 by Michael G. Morrow.  All rights reserved.
///////////////////////////////////////////////////////////////////////

#include "DSK_Support.h"   
#include "c6711cfg.h"

void EdmaStartUp()
////////////////////////////////////////////////////////////////////////
// Purpose:   Configure EDMA controller to perform all McBSP servicing. 
//            EDMA is setup so buffer[2] is outbound to McBSP, buffer[0] is 
//            available for processing, and buffer[1] is being loaded.
//            Both the EDMA transmit and receive events are set to automatically
//            reload upon completion, cycling through the 3 buffers. 
//            The EDMA completion interrupt occurs when a buffer has been filled
//            by the EDMA from the McBSP.
//            The required McBSP is setup and enabled.
//
// Input:     None
//
// Returns:   Nothing
//
// Calls:     Nothing
//
// Notes:     None
///////////////////////////////////////////////////////////////////////
{
	int i;
	#define NUM_AIC23_REGISTERS 10
	short AIC23_data[NUM_AIC23_REGISTERS] = {
		0x017, // reg 0 - left line volume (0 db)
		0x017, // reg 1 - right line volume (0 db)
		0x0f9, // reg 2 - left headphone volume (0 db)
		0x0f9, // reg 3 - right headphone volume (0 db)
		0x012, // reg 4 - analog audio path (DAC on, line input)
		0x000, // reg 5 - digital audio path (no deemphasis)
		0x000, // reg 6 - power down (all on)
		0x053, // reg 7 - digital audio interface (DSP mode)
		0x001, // reg 8 - sample rate (48kHz)
		0x001  // reg 9 - digital interface (activate)
	};
	
	/* Update all the buffer sizes just in case BUFFER_COUNT has changed. */		
	edmaCfg_Rx0.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Rx0.rld = (edmaCfg_Rx0.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);
	edmaCfg_Rx1.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Rx1.rld = (edmaCfg_Rx1.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);
	edmaCfg_Rx2.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Rx2.rld = (edmaCfg_Rx2.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);

	edmaCfg_Tx0.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Tx0.rld = (edmaCfg_Tx0.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);
	edmaCfg_Tx1.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Tx1.rld = (edmaCfg_Tx1.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);
	edmaCfg_Tx2.cnt = (0 << 16) + (BUFFER_COUNT);
	edmaCfg_Tx2.rld = (edmaCfg_Tx2.rld & 0x0000ffff ) | (BUFFER_COUNT << 16);

    EDMA_config(hEdmaTbl_Tx0, &edmaCfg_Tx0);
    EDMA_config(hEdmaTbl_Tx1, &edmaCfg_Tx1);
    EDMA_config(hEdmaTbl_Tx2, &edmaCfg_Tx2);
    EDMA_config(hEdmaTbl_Rx0, &edmaCfg_Rx0);
    EDMA_config(hEdmaTbl_Rx1, &edmaCfg_Rx1);
    EDMA_config(hEdmaTbl_Rx2, &edmaCfg_Rx2);

	if(CodecType == TLC320AD535) {
		EDMA_reset(hEdmaCha13);
		EDMA_reset(hEdmaCha12);
		EDMA_config(hEdmaCha13, &edmaCfg_Rx1);
		EDMA_config(hEdmaCha12, &edmaCfg_Tx2);
		EDMA_enableChannel(hEdmaCha13);
		EDMA_enableChannel(hEdmaCha12);
  		EDMA_intEnable(15); 		// enable EDMA irq for TCC code 15 
  	}
  	else {
		EDMA_reset(hEdmaCha15);
		EDMA_reset(hEdmaCha14);
		EDMA_config(hEdmaCha15, &edmaCfg_Rx1);
		EDMA_config(hEdmaCha14, &edmaCfg_Tx2);
		EDMA_enableChannel(hEdmaCha15);
		EDMA_enableChannel(hEdmaCha14);
	  	EDMA_intEnable(15); 		// enable EDMA irq for TCC code 15 
	}
  	C62_enableIER(0x0100);			// enable EDMA irqs
  									// reset and start-up McBSP
  	switch(CodecType) {
  	case eDSP_PCM3006:
	  	MCBSP_config(hMcbsp1, &mcbspCfg_eDSP_PCM3006);
  		MCBSP_enableSrgr(hMcbsp1);
  		MCBSP_enableFsync(hMcbsp1);
    	MCBSP_enableXmt(hMcbsp1);
    	MCBSP_enableRcv(hMcbsp1);
      	break;
  	case TI_PCM3003_16bit:
    	MCBSP_config(hMcbsp1, &mcbspCfg_TI_daughtercard);
    	MCBSP_enableXmt(hMcbsp1);
    	MCBSP_enableRcv(hMcbsp1);
      	break;
    case DSK6713_16bit:
    	MCBSP_config(hMcbsp0, &mcbspCfg_AIC23_control);
  		MCBSP_enableSrgr(hMcbsp0);
  		MCBSP_enableFsync(hMcbsp0);
    	MCBSP_enableXmt(hMcbsp0);
		for(i = 0;i < NUM_AIC23_REGISTERS;i++) { // program codec
			while(!(MCBSP_xrdy(hMcbsp0))) 
				;
			MCBSP_write(hMcbsp0,(i << 9) | AIC23_data[i]); // write codec registers
		}
		while(!(MCBSP_xempty(hMcbsp0))) // wait for McBSP0 to finish
			;
        MCBSP_config(hMcbsp1, &mcbspCfg_AIC23_data); // start data channel
    	MCBSP_enableXmt(hMcbsp1);
    	MCBSP_enableRcv(hMcbsp1);
    	break;
    default: // must be 6711 onboard codec
    	MCBSP_config(hMcbsp0, &mcbspCfg_TLC320AD535);
    	MCBSP_write(hMcbsp0,0); // ensure first xmit is 0
    	MCBSP_enableXmt(hMcbsp0);
    	MCBSP_enableRcv(hMcbsp0);
    }

}