Handouts
PLD General Design Flow
Verilog
Directions to downloading the Cadence NC-Simulator
Gradual Introduction to Verilog:
Combinational
and
Sequential
On-line Verilog HDL Quick Reference Guide
by Stuart Sutherland
Verilog Template Maker
(note: the UCF maker is for the XS-40 board only)
Transmission Line Effects
Transmission Line Effects on a Bus
(Java applet)
Miscellaneous
grid paper for timing diagrams:
portrait
grid paper for timing diagrams:
landscape