4 Digit 7-Segment Display Generator
Introduction
This laboratory will give you confidence to use the CAD tools associated with targeting a Verilog description to a Xilinx FPGA. The Xilinx FPGA development kit contains 3 boards.
(i) a main controller board containing the Xilinx FPGA and a 50MHz clock system,
(ii) an I/O board that contains a series of switches, buttons, LEDs, and a 4-digit 7-segment display
(iii) a breadboard that may be used for external stimuli and analog components)
In this lab, you will be using the main controller board and the I/O board. You will design a character message that can be displayed on the 4-digit 7-segment display. The message must be at least 2 characters long and can be as long as 4 characters. You can use numbers, letters, or any character of your design. Be creative. Be certain to read the users manual of the I/O board before designing your circuit so that you know how to properly drive the 7-segment display and handle the refresh rate appropriately. Also, look at the functionality of the push buttons so that you will know whether the reset for your system should be active high or active low. (The switches cannot be used currently because they must be debounced. We will discuss how to debounce switches in a couple of weeks.)
A few notes about the 7-segment display:
1) All 12 signals (4 enables for each digit, the cathodes of each of the 7 segments, and the cathode of the decimal point) of the 7-segment display must be activated to something at all times.
2) The display must be tied to the master reset, so that when the reset is activated, all segments are turned off.
3) The entire system must be driven by the 50MHz master clock. You can divide this clock down to the frequency necessary by the refresh rate. The verilog code given to you in the sequential notes may be used to do the clock division. If your system is driven by the clock edge, you do not need a 50% duty cycle for your system to operate correctly.
Objectives
 | Gain confidence with new design tools for the FPGA |
| Implement a seven-segment decoder for the 4-digit seven-segment LED |
Parts List
No additional parts required for this lab. Everything is contained in the development kit.
Equipment
| Spartan2E FPGA evaluation board kit (can be checked out from the instrument room) |
Software
| Xilinx ISE FPGA implementation tools |
| Cadence NC-Simulator behavioral simulator for Verilog |
Prelab
- Check out one Spartan2E FPGA evaluation kits from the Instrument Room
(only one per lab group). Your kit should contain the controller board, an I/O
board, a
breadboard, a 9-volt plug-in power supply, and a parallel port cable.
- Review the users manual of the I/O board. All of the Xilinx board
descriptions can be found at the following web site:
www.digilentinc.com. Use the
"Products" tab to access the peripheral boards to find the I/O board. We are
using the IO1 board. Choose "more information" to get to the page that
contains the link to the users manual.
- Design the truth table necessary to drive each of the 7 segments for your
character set. Please tell me what the character set is supposed to look like
if it were illuminated by the seven-segment display.
- Calculate the refresh rate necessary for your design.
- Calculate the size of the counter necessary to obtain your refresh rate
from the 50MHz clock.
- Write the Verilog code for your design (note: you may want to use a
parameterized statement for the max count and make it much smaller for the
simulation. Otherwise, the simulation will take a HUGE amount of time. Be sure
to change it back before you come into lab on Wed.) Turn in your .v file.
- Write the testbench to verify your design. Turn in your testbench file.
- Provide an annotated timing diagram displaying your results.
- Study carefully the
Design Flow: Verilog, FPGA document. This is your roadmap for the design, verification, and
implementation process. The first part is identical to the GAL design flow.
You may skip this part and begin at the section titled: Convert Your
Design Files to Produce a bitstream File.
- A photocopy of your prelab pages is due at the beginning of the class the day before lab.
Lab
NOTE: If you need a "sanity test" of your Xilinx board, download count4.v and count4.ucf. Generate the bit file and download it to the board. You should see 4 LED lights counting in binary from 0 to 15.
- Carry out the complete implementation process for your character
generator.
- Demonstrate your character generator circuit to the instructor.
All done!
| Clean up your work area |
| Remember to submit your lab notebook for grading at the beginning of next week's lab |