Design Project Tips

ECE333: Digital Systems

General

	The Tip	Why It Helps	Problems When Not Followed
G1	Start working on your design NOW! Ask questions!	Finish on time Satisfaction and self-confidence	Frustration Panic
G2	Learn how to recognize when you need more information	Designing, building, and troubleshooting systems yourself is part of your learning process. However, don’t “spin your wheels” for hours at a time. Seek assistance!	Wastes time, causes frustration and unhappiness As an engineer you will be expected to be self-directed and be able to get things done without bothering your manager too much. However, you will not look good if you fail to seek help from your manager or others, and spend a lot of hours in unproductive activity.

Design and Initial Build

	The Tip	Why It Helps	Problems When Not Followed
D1	Draw your complete hardware diagram first, then write Verilog descriptions for each hardware block. Use separate ‘always’ module for each block. Do not assign values to the same signal in multiple ‘always’ blocks.	If you can’t describe your hardware as a block diagram, then you shouldn’t waste your time trying to describe it to a CAD tool	Try to invent unrealizable hardware Unclear timing relationships between systems Waste time creating Verilog description that is likely to fail when synthesized to hardware
D2	Draw the state transition diagram first, then translate into Verilog	Helps you to think through the timing relationships	Unclear timing relationships between systems Glitches, unreliable behavior
D3	Spend most of your time with the simulator, not with the hardware	The simulator lets you test and verify your system easily You can try new ideas and see the results (iterate) almost instantly	System debugging becomes increasingly time consuming between iterations the closer you get to the hardware
D4	Build and test small pieces individually, then integrate the pieces together	Smaller pieces are easier to test and verify for correction operation Integrated system has higher chance of correct operation the first time	Difficult to identify what is wrong by observing only the final output Applying power to the system all at once may result in smoked chips due to chronic wiring errors
D5	Use a standard naming scheme for inputs, outputs, “reg” identifiers, parameters, and so on	Helps you organize your design Makes code more readable (enhances portability and maintainability) Easier to locate signals in CAD tool listings
D6	Behavioral simulator tip: Learn how to “push down” into lower levels to view internal signals	The simulator lets you view all possible signal activity in your design. When a particular signal doesn’t behave as you expect, trace backwards to isolate the source of the problem.	It is usually impossible or very difficult to isolate an internal problem by looking only at the primary output signals.

Good Practice for Digital Systems

	The Tip	Why It Helps	Problems When Not Followed
P1	All flip-flop clock inputs should connect to the master clock In Verilog: All sequential ‘always’ blocks should trigger on the master clock. Use “clock enable” signals to cause action to occur when desired	Eliminates possibility of unreliable operation due to gated clocks	Potential exists for spurious, erratic, and undesired operation (very difficult to troubleshoot)
P2	All flip-flops should have asynchronous reset connected to master reset	Gives you ability to force all flip-flops to a known state (especially helpful during simulation)	Sometimes “X”s (unknowns) will suddenly appear in your simulation, alerting you to a problem. If you begin the simulation with all flip-flops in a known state, then it is easier to trace the source of the problem.
P3	Synchronize all inputs that are used to make control decisions	Reduces risk that an input transition that occurs near a clock edge will cause incorrect behavior	Finite state machine randomly goes to wrong state (extremely difficult to troubleshoot!)
P4	Signals sent off-chip should be derived from flip-flop outputs instead of combinational logic	Guarantees glitch-free outputs	Some devices may not work reliably if you send them glitchy signals

Good Practice for Digital Systems Described in Verilog HDL

V1	Verilog ‘always’ blocks for combinational circuits should look like this: always @ (in1 or in2 or ... or InN) begin Be sure to list all possible input signals that will be used by the circuit Output values assigned should account for all possible input combinations, otherwise you will see “inferred latch” warnings in FPGA implementation tool Do not assign values to a given output in more than one “always” block end
V2	Verilog ‘always’ blocks for sequential circuits should look like this: always @ (posedge MasterClock or posedge MasterReset) if (MasterReset) begin Assign output values that should occur upon reset signal end else begin Assign output values that should occur on the next clock edge Use “enabling signals” to cause desired activity end
V3	Use Verilog “parameter” statement to define terminal count value for a clock divider circuit Use small terminal count value during simulation Use correct value for synthesis	Speeds up simulation time (not necessary to wait hundreds or thousands of clock cycles for each pulse from the clock divider)	Waste a lot of simulator time. Difficult to identify interesting behavior amidst all the clock cycles between
V4	Use action statements to name control signals Examples: “InitializeCounter”, “EnableShifting”, “InvertTheOutput” ... as opposed to “INIT”, “EN”, “INV”	Improves readability of your code Signal name tells you what action is taking place Works best when you use a consistent assertion level such as “active high” For example: “InitializeCounter = 1” is more intuitive than “INIT = 1”	Your code may be difficult to interpret by others (hampers portability) Your own code may become difficult to interpret after a long time period has elapsed (hampers maintenance)
V5	Use short sentences to name status signals Examples: “CountSequenceIsDone”, “MicroIsNotReady”	see previous	see previous

Hardware and CAD Tools

	The Tip	Why It Helps	Problems When Not Followed
H1	Be careful with XS-40 board! XC4010XL FPGA is a 3.3V device (output voltages are 0 to 3.3V) Input pins expect 3.3V, but are 5V-tolerant	A 100% functional FPGA eliminates a source of error when troubleshooting The FPGA is not cheap... about $40 value	Defective FPGA may appear to be fine most of the time, then “act up” occasionally Worst case (obviously) is that you let out the “magic smoke”
H2	Learn how to specify pin locations to your CAD tool Learn how to determine pin assignments made by CAD tool	Random pin assignments are not useful when you have external resources pre-wired to the FPGA	FPGA may appear unresponsive to changes in input, or the outputs change in unexpected ways
	Specify pins: Xilinx Foundation Series: In “Implementation” step, choose “SET”, then “Use Custom UCF”, then specify your .UCF file (do this every time you do the implementation step) Lattice ispDesignEXPERT: When doing GALs, simply specify the pin numbers in the schematic or ABEL file. When doing CPLDs, use “Tools” followed by “Import Constraints”, then enable the “import constraints from source” option. Review pin assignments made by CAD tool: Xilinx Foundation Series: In Project Manager, choose “Reports, Pad Report” Lattice ispDesignEXPERT: Look for “chip report” or “post-fit pinout” report
H3	Use staples (standard half-inch) to make power and ground connections on breadboard Also useful for tying unused inputs to ground or power Be careful, though: Make sure there is no plastic residue on the staple! [Acknowledgement to Dr. Bill Eccles for this idea]	Saves wiring time Makes a neater board layout	Circuit construction takes longer