;******************************************************************************
;    ECE331 Lab 3 Part 4 
;    File: outchartst.asm (by KEH) 
;    Tests outchar routine
;******************************************************************************
            XDEF outchartest        ; Export 'program entry point' symbol
  
            ABSENTRY outchartest         ; For absolute assembly: mark this as application entry point
            INCLUDE 'mc9s12c32.inc'	; Include 9S12C32 register symbol definitions.
            ORG $4000
outchartest:lds  #$3F00             ; Initialize program stack pointer just below UBUG12 stack.
            jsr init_pll
            ldx #10
agn:        ldab #'a'
            jsr outchar
            dex
            bne agn
wthr:       bra wthr

init_pll:         
  ;****Initialize clock generator and PLL for 24 MHz internal bus clock***********
  ;This initialization is performed by the serial debugger UBUG12, but it is not 
  ;performed when a user program is run by itself (out of RESET without the serial debugger
  ;In that case, the internal clock defaults to 16/2 = 8 MHz.  That is why I have included this 
  ;code in this program... since we want the delay routine and the serial port baud rate to remain 
  ;the same whether we are running under the debugger or without it!
  ;
  ;NOTE: This PLL initialization section may NOT be single stepped through using the serial debugger, 
  ;      since the bus clock changes, and thus so does the serial port baud rate change 
  ;      as the PLL is disconnected from the system.
  ;
	          bclr	CLKSEL,$80        	;disconnect PLL from system
	          bset	PLLCTL,$40       	  ;turn on PLL

	          movb	#2,SYNR     	      ;set PLL multiplier 
	          movb	#1,REFDV   	        ;set PLL divider
	          ;PLLCLK = OSCCLK*(SYNR+1)/(REFDV+1)= 16MHz *(2+1)/(1+1) = 24MHz
	          nop			;NOP delays put here to allow time for  	          	
            nop			;CRGFLG flag register to become valid.
wt_PLL_Lock:	
	          brclr	CRGFLG,8,wt_PLL_Lock ;Wait for PLL to lock	  
	          bset	CLKSEL,$80      	   ;Connect PLL into system
  ;*********End of PLL initialization. Now module clk = 24 MHz!
  ;*******************************************************************************            
            rts          
outchar:
; Subroutine outchar --- outputs to serial port contents of B
; sets port to 9600 baud, 8 bits, no parity, 1 stop bit
            movb #156,SCIBDL
            clr SCIBDH          ;9600 baud
            clr SCICR1       ;8 data, no parity, 1 stop bit
            movb #%00001100,SCICR2; enable tx, rx enabled, no interrupts
wt_tdre:    brclr SCISR1,%10000000,wt_tdre; wait for TDRE to be set
            stab SCIDRL           ;send char
            rts
            
               
            
  		        ORG       $FFFE
            	fdb  outchartest     ; Initialize Reset Vector