; export symbols  (to be referenced outside of this file)
            XDEF INIT_PLL           
            INCLUDE 'mc9s12c128.inc'
MyCode:     SECTION
INIT_PLL:
              ;*********Initialize clock generator and PLL
	          bclr	CLKSEL,$80        	;disengage PLL from system
	          bset	PLLCTL,$40       	  ;turn on PLL

	          movb	#5,SYNR     	      ;set PLL multiplier 
	          movb	#0,REFDV   	        ;set PLL divider
	          ;From Section 3.1.1 of CRG Block Guide					
	          ;PLLCLK = OSCCLK*(SYNR+1)/(REFDV+1)				
	          ;       = 4 MHz * (5+1)/(0+1) = 24 MHz
	          nop			         ;NOP delays put here to allow time for  	       
	          nop
            nop			         ;the CRGFLG flag register to become valid.

wt_PLL_Lock:	
	          brclr	CRGFLG,8,wt_PLL_Lock    	  
	          bset	CLKSEL,$80      	  ;engage PLL into system
  ;*********End of PLL initialization. Now module clk = 24 MHz!
            RTS
            END