Transforming Your Concept into an FPGA Bitfile: Step-by-Step Instructions

E.R.Doering

October 29, 2001

Software versions for this document:

· Silos 2001 demo version (http://www.simucad.com/)

· Xilinx Foundation Series version 2.1i (packaged with Wakerly’s textbook)

· XSTOOLS (http://www.xess.com)

· XS-40 FPGA Development Board ver. 1.4

What to Do:	How to Do It:	Comments:
Create Conceptual Design:
Draw I/O block diagram of your circuit, i.e., draw a rectangle with pins sticking out, and write a name for each pin (signal). If you are targeting the XS40 board for stand-alone FPGA operation, add pins called “o$MicroReset” and “o$RAMOE_” (or equivalent... the underscore denotes an active-low signal).	Use a piece of paper, and a pen or pencil :-)	You will find it helpful to clarify some basic details before you jump in with the computer tools. Tip: Use “i$” as a prefix for all your input names and “o$” as a prefix for all your output names to improve readability of your Verilog code and other auto-generated files. Regarding the two extra pins: The XS40 includes a variety of peripheral devices that are permanently connected to the FPGA. Holding the 8031 microcontroller reset pin high will deactivate the micro and force all of its pins to high-impedance mode. Holding the RAM output enable high likewise tristates the RAM output pins.
Draw high-level diagram of your circuit.	See above.	The diagram will help you visualize the hardware when you write your circuit descriptions.
Enter Your Design:
Create a Verilog template for the circuit and testbench. Use the Verilog Template Maker (VTM).	See http://www.rose-hulman.edu/~doering/php/vtm.php	Enter the number of input and output ports. Bit vectors (busses) count as a single port. Next, enter the information specific to your design (module name, port names). Verilog Template Maker will return a text listing that you can copy and paste into a text editor.
Generate the circuit template.	Select the “Make Circuit” option, then copy the resulting text into a file called name.v.	name.v will contain your circuit, the part that will end up in the FPGA.
Generate the testbench template.	Hit your browser’s “Back” button, then select the “Make Testbench” option. Copy the resulting text into a file called name_TB.v	name_TB.v will contain your testbench, the part that exercises your circuit in a behavioral simulator.
Generate the UCF file (user constraints file).	Hit your browser’s “Back” button, then select the “Make UCF” option. Select the XS-40 resources that you require for your design, then match your specific pins to specific resources. Copy the resulting text into a file called name.ucf	This file will be used later.
Enter the circuit description and testbench simulation.	Enter your Verilog text into the two .v files.	Add additional comments (documentation) into the .v files as needed. NOTE: VTM assumes all outputs will be ‘reg’ identifiers. If you need to use continuous assignment (by using an ‘assign’ statement), then simply delete or comment out the associated ‘reg’ declaration. TIP: You may wish to use the Silos text editor... select “File | New”, copy/paste the text from VTM, then save to a .v file (you need to specify the .v file suffix yourself). Also, the Silos text editor includes an option to color code the text file according to Verilog syntax... select “Options | Syntax Color Coding”.
Verify Your Design Using Simulation:
Create a new project in Silos (Verilog behavioral simulator).	After starting Silos, select “Project | New”, then enter a name for your project.	Tip: Create a new folder for your project, then all related files will be stored in the same place. In B-200, use the C:\student directory.
Add your two Verilog files to the project.	Silos will pop up a new window after creating the project. Navigate to the location of your .v files, and double click each file to add to the project. Click “OK” when finished.
Run your simulation.	Press the “GO” button. If all goes well, you will see some commentary followed by the “Ready:” prompt.
View the simulation results as a timing diagram.	Press the “Open Explorer” and “Open Analyzer” buttons. In the Data Explorer window, single click the module name (it should be the same name as your testbench module). Click and drag the signal names from the Data Explorer window to the Data Analyzer window.	Once the timing diagram is visible (and the Data Analyzer window is selected), use the toolbar helpers as needed, e.g., zoom in, zoom out, full screen, etc. Change the display of bus values from hexadecimal to something else (decimal, binary, etc.) by right-clicking on a signal name and choosing “Set Radix”.
Iterate until your design is correct.	Press “File | Open” to open your .v file(s) using the Silos editor. After updating your file by using Ctrl-S, press Alt+F5 key combination to reload the files and resimulate. Repeat the design/debug cycle as needed.	Tip: You may find it convenient to use the “Window | Tile” mode. <= One of the most powerful features of Silos! Very short turnaround time from circuit change to simulation result.
Implement Your Design to Produce an FPGA Bitstream File:
Create a new project in Xilinx Foundation Series.	Start Xilinx Foundation Series. Select “Create New Project” radio button. Select “HDL” project (this is important!) and enter project name (8 chars max).	Tip: Choose your own directory for the project.
Add Verilog circuit file to the project.	Select “Project | Add Source File(s)” in the Project Manager window. Navigate to your name.v Verilog file. Do NOT add the testbench file name_TB.v.	Foundation will add a copy of your .v file to your Xilinx project directory, and will analyze the Verilog file to check for errors. It is possible to write a Verilog description that simulates successfully in Silos, and yet is incompatible in some way with the hardware synthesis of Foundation. This is not necessarily a shortcoming of Foundation, but rather due to the fact that Verilog is inherently a simulation and modeling language, and hardware synthesis only deals with a subset of the language. Bottom line: Learn how to write synthesizable descriptions!
Synthesize hardware.	Click the “Synthesis” button on the right side of the Project Manager window. Ensure that the top-level module name is correct, especially if you are doing a multi-module design. Set target device family to “XC4000XL”. Set target device to “4010XLPC84” Set the speed grade to “xl-3”. Click “Run” to begin the synthesizer.	This step converts your Verilog description into a netlist, a set of files that describe the devices and interconnections needed by your design. Synthesis makes your design specific to a particular target device. Hopefully you will not see any fatal error messages (in red) or warnings (in blue). All warnings should be dealt with, and fix the problems beginning with the first warning. Often fixing the first problem will fix many other problems, too. Double-click the .v file listed in the upper left of the Project Manager window to edit the file (remember, this file is now part of the Foundation project directory, so it will not help to edit the original .v file used for simulation). Here are some common warnings: 1. “inferred latch” -- should cause you to look for places in your design where the output of a combinational circuit behavior is not completely specified for all possible input combinations, 2. “outputs wired together” -- look for places where the same output signal as assigned values in two or more ‘always’ blocks or by two or more ‘assign’ statements, 3. “I/O pin has no connections” -- the synthesis tool removes circuitry that it believes is never used (for example, the output of the circuit doesn’t lead to any other circuit input)... study your code and try to learn why the circuit connected to the signal named in the warning doesn’t do anything.
Create a User Constraints File (UCF) NOTE: Only do this step if you did not earlier use VTM to create the UCF!	Click the “Implementation” button on the right side of the Project Manager window. Click “Run”. Select “Tools | Implementation | Lock Device Pins”. Use Windows file system to navigate to the Foundation project directory. Continue into the “xproj\ver1\rev1” directory. Find the .UCF file and copy it to another directory of your own. Verify that your pin list shows up at the bottom of the .UCF file. Delete all the remaining boilerplate comments (all lines beginning with ‘#’). Add your own comments to the top of the .UCF file.	NOTE: This step is the long way around, but it guarantees that your UCF will be syntactically correct and that no I/O pin names are missing and that no extraneous I/O names are added. You only need to do this step if you have no UCF in place. If you are confident in creating your own UCF, or you are using a previous UCF as a model, then you can skip this step.
Edit UCF for your specific design. NOTE: Only do this step if you did not earlier use VTM to create the UCF!	Adjust the pin numbers to reflect your design intent. Refer to the “Simplified XS40 Schematic” (page 18 in the XS40 ver. 1.4 user’s manual) to determine what pins are available and where the peripheral devices connect. If this is a stand-alone FPGA design, then connect i$MicroReset” to Pin 36, and “o$RAMOE_” to Pin 61.
Create a new “revision” of your implementation. NOTE: Only do this step if you did not earlier use VTM to create the UCF!	If you followed the previous step, then you have a “version 1” (from synthesis) and a “revision 1” (from implementation). Select “Project | Delete Revision” in the Project Manager window to clear all information associated with the previous implementation.
Implement your design to create a bitstream file.	Click the “Implementation” button. Press the “SET” button at the bottom of the popup window. Select “Custom” for the “Use constraints file from” option, then specify your own UCF file. DO THIS EACH TIME YOU RUN IMPLEMENTATION! Click “Run” when finished. Once implementation is complete, select the “Reports” tap (upper right side of Project Manager window), followed by “Implementation Reports.” The Map Report tells you device utilization (percent CLBs used, etc.) and the Pad Report tells you where the I/O signals appear among the 84 pins.	A very common problem is losing track of the UCF file, especially when you make repeated changes and revisions to your design. You need to ensure that you have control over how the signals connect to the pins, otherwise a random selection will be made for you.
Download the FPGA Bitstream File to XS40 Board:
Ensure that the XS40 board is powered and is connected by parallel cable to the computer’s parallel port.
Locate the bitstream file	Use Windows system to navigate to your Foundation project directory, then locate the .BIT file.
Launch the XS40 download application	Run the GXSLOAD application.
Download the bitstream file.	Drag the .BIT file to the GXSLOAD application.	NOTE: GXSLOAD operates “open loop”, meaning that it does not receive any communication from the XS40 board. Thus, GXSLOAD may report that all is well, even when the XS40 board is not powered or when the parallel cable is disconnected. TIP: Make or obtain a simple test bitstream that can give you a sanity test check (such as lighting the LED segments in a particular way).
Test Your Design:
Apply external stimulus from your own circuitry.	The FPGA on the XS40 board operates at 3.3 volts. The inputs are 5-volt tolerant.
Apply external stimulus from the computer parallel port cable.	Run the GXSPORT application. The eight signals are connected directly to the FPGA and can serve as external stimulus.	NOTE: You need to use a special Verilog technique in order to make your design responsive to the upper two bits from the parallel port. If you get to this point, ask for help!
Change the XS40 clock frequency if needed.	Run the GXSSETCLK application. Follow the instructions carefully, since you will need to adjust a jumper setting as part of the process.	You can specify an integer divider factor. For example, if you want the clock frequency to be 12 MHz, use a divisor of 8.