FPGA | XC4010XL | XS40 | Foundation Series | Verilog | VeriLogger

This section is still under development...

NOTE: This design flow is identical to the FPGA/Verilog Design Flow based on Silos III, except for using VeriLogger as the HDL simulation tool. FPGA-based designs are generally more complex, and thus require more effort to design a useful set of input stimuli. Since the demo version of VeriLogger will not save project files, you would be unable to continue development of functional tests across multiple sessions of VeriLogger. Therefore, you should use the "testbench" style of functional verification that is used by Silos III. Please continue with the FPGA/Verilog Design Flow.

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Page last updated December 21, 1999. Feedback goes to Ed.Doering@Rose-Hulman.Edu.