Design Flow for CPLD / Verilog / Silos III
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CPLD | MACH4 64/32 | Vantis ISP Board | Vantis Design Direct | Verilog | Silos III

Step 7: Follow the design flow below, or go back to previous step:

[NOTE: Click on each block in the flow diagram to watch the step-by-step process of a complete design example]

 

formulate_concept_gal.gif (1542 bytes)paper_and_pencil.gif (1267 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
develop_specs_gal.gif (1617 bytes)paper_and_pencil.gif (1267 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
create_architecture_gal.gif (1557 bytes)paper_and_pencil.gif (1267 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
describe_arch_gal.gif (1748 bytes)silosiii.gif (1275 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
verify_functionality_gal.gif (1765 bytes)silosiii.gif (1275 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
synthesize_hardware.gif (1734 bytes)designdirect.gif (1441 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
map_design_gal.gif (1727 bytes)designdirect.gif (1441 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
configure_device_gal.gif (1626 bytes)designdirect.gif (1441 bytes)
down_arrow.gif (1122 bytes)space.gif (986 bytes)
verify_insystem_gal.gif (1764 bytes)instrumentation.gif (1473 bytes)

Supplements to the design flow example:

Design Direct zipped project files, including JEDEC downloadable file

Verilog source file and testbench file

 

Page last updated December 18, 1999. Feedback goes to Ed.Doering@Rose-Hulman.Edu.