Step 1: Choose one of the following PLD families, or go back to previous
step:
[Watch Me to see what the devices look
like, and to learn proper handling techniques to avoid ESD damage]
- GAL
- -- Generic Array Logic
-- PAL architecture with capability of flip-flop or combinational outputs
-- Programmed by a ROM "burner", and is electrically erasable
-- Relatively low complexity
- CPLD
- -- Complex Programmable Logic Device
-- Array of interrconnected GALs (called macrocells) on a single chip
-- Programmable without removing from its circuit
-- Maintains programming when power is removed
-- Moderate complexity
-- Best suited to designs that have lots of random logic and few flip-flops
- FPGA
- -- Field-Programmable Gate Array
-- Array of configurable logic blocks (CLBs)
-- Programmable without removing from surrounding circuitry
-- Loses programming when power is removed
-- Relatively high complexity
-- Best suited to designs that have low random logic and lots of flip-flops
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