//
// Written by Synplify
// Fri Oct 27 17:19:02 2000
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\isptools\synplify\lib\cpld\lattice.v "
// file 2 "\c:\isptools\ispsys\generic\verilog\synplify\generic.v "
// file 3 "\c:\isptools\ispsys\examples\mach_pal\verilog\traffic\traffic.v "

`timescale 100 ps/100 ps
module MACH_DFF (
  Q,
  D,
  CLK,
  R,
  S,
  NOTIFIER
);
output Q;
input D;
input CLK;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  reg r_e_g0; // dffrs
  always @(posedge CLK or posedge un1 or posedge un0 )
    r_e_g0 = #1 un1 ? 1'b0 : (un0 ? 1'b1 : D );
  assign Q = r_e_g0;
endmodule /* MACH_DFF */

module DFFRH (
  Q,
  D,
  CLK,
  R
);
output Q;
input D;
input CLK;
input R;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire un0 ;
wire un1 ;
wire true ;
wire notifier ;
wire false ;
  MACH_DFF INS1 (
	.Q(un0),
	.D(D),
	.CLK(CLK),
	.R(un1),
	.S(true),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFFRH */

module IBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IBUF */

module OBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* OBUF */

module AND2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module INV (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = ~ I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module XOR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  ^ I1 ;
endmodule /* XOR2 */

module traffic (
  clock,
  reset,
  sensor1,
  sensor2,
  red1,
  yellow1,
  green1,
  red2,
  yellow2,
  green2
);
input clock;
input reset;
input sensor1;
input sensor2;
output red1;
output yellow1;
output green1;
output red2;
output yellow2;
output green2;
wire clock ;
wire reset ;
wire sensor1 ;
wire sensor2 ;
wire red1 ;
wire yellow1 ;
wire green1 ;
wire red2 ;
wire yellow2 ;
wire green2 ;
wire [1:0] state;
wire [2:0] nxstate_20;
wire [0:0] state_i;
wire [2:2] state_c;
wire [2:2] state_i_c;
wire N_60 ;
wire N_61 ;
wire N_62 ;
wire N_68 ;
wire N_69 ;
wire N_70 ;
wire N_71 ;
wire N_72 ;
wire N_74 ;
wire N_75 ;
wire N_76 ;
wire sensor2_i ;
wire sensor1_i ;
wire clock_c ;
wire reset_c ;
wire sensor1_c ;
wire sensor2_c ;
wire yellow1_c ;
wire yellow2_c ;
wire yellow1_c_i ;
wire N_79 ;
wire N_70_i ;
wire N_71_i ;
wire N_72_i ;
wire N_81 ;
wire N_68_i ;
wire N_69_i ;
wire N_82 ;
wire N_62_i_c ;
wire N_47_i_c ;
wire N_61_i_0 ;
wire N_86 ;
wire N_87 ;
wire N_88 ;
wire GND ;
wire VCC ;
// @3:39
  DFFRH \state_Z[0]  (
	.Q(state[0]),
	.D(nxstate_20[0]),
	.CLK(clock_c),
	.R(reset_c)
);
// @3:39
  DFFRH \state_Z[1]  (
	.Q(state[1]),
	.D(nxstate_20[1]),
	.CLK(clock_c),
	.R(reset_c)
);
// @3:39
  DFFRH \state[2]  (
	.Q(state_c[2]),
	.D(nxstate_20[2]),
	.CLK(clock_c),
	.R(reset_c)
);
  IBUF clock_Z (
	.O(clock_c),
	.I0(clock)
);
  IBUF reset_Z (
	.O(reset_c),
	.I0(reset)
);
  IBUF sensor1_Z (
	.O(sensor1_c),
	.I0(sensor1)
);
  IBUF sensor2_Z (
	.O(sensor2_c),
	.I0(sensor2)
);
  OBUF red1_Z (
	.O(red1),
	.I0(state_c[2])
);
  OBUF yellow1_Z (
	.O(yellow1),
	.I0(yellow1_c)
);
  OBUF green1_Z (
	.O(green1),
	.I0(N_47_i_c)
);
  OBUF red2_Z (
	.O(red2),
	.I0(state_i_c[2])
);
  OBUF yellow2_Z (
	.O(yellow2),
	.I0(yellow2_c)
);
  OBUF green2_Z (
	.O(green2),
	.I0(N_62_i_c)
);
  AND2 \nxstate_20_0_and2_1.G_71  (
	.O(N_86),
	.I0(state_c[2]),
	.I1(sensor2_i)
);
  AND2 \nxstate_20_0_1.G_72  (
	.O(N_87),
	.I0(N_68_i),
	.I1(N_69_i)
);
  AND2 \nxstate_20_0_0.G_73  (
	.O(N_88),
	.I0(N_70_i),
	.I1(N_72_i)
);
  INV green2_8_i_0_or2_i (
	.O(N_62),
	.I0(N_62_i_c)
);
  INV G_63_i (
	.O(N_61),
	.I0(N_61_i_0)
);
  INV yellow1_c_i_Z (
	.O(yellow1_c_i),
	.I0(yellow1_c)
);
  INV \nxstate_20_xor2_0_i[2]  (
	.O(nxstate_20[2]),
	.I0(N_79)
);
  INV N_70_i_Z (
	.O(N_70_i),
	.I0(N_70)
);
  INV N_71_i_Z (
	.O(N_71_i),
	.I0(N_71)
);
  INV N_72_i_Z (
	.O(N_72_i),
	.I0(N_72)
);
  INV \nxstate_20_0_i[0]  (
	.O(nxstate_20[0]),
	.I0(N_81)
);
  INV N_68_i_Z (
	.O(N_68_i),
	.I0(N_68)
);
  INV N_69_i_Z (
	.O(N_69_i),
	.I0(N_69)
);
  INV \nxstate_20_0_i[1]  (
	.O(nxstate_20[1]),
	.I0(N_82)
);
  AND2 \nxstate_20_0_and2[1]  (
	.O(N_68),
	.I0(N_76),
	.I1(N_86)
);
  AND2 \nxstate_20_0[0]  (
	.O(N_81),
	.I0(N_71_i),
	.I1(N_88)
);
  AND2 \nxstate_20_0[1]  (
	.O(N_82),
	.I0(N_60),
	.I1(N_87)
);
  AND2 \nxstate_20_0_and2_1[0]  (
	.O(N_72),
	.I0(N_74),
	.I1(N_76)
);
  AND2 green2_8_i_0_or2 (
	.O(N_62_i_c),
	.I0(state_c[2]),
	.I1(N_61)
);
  INV \state_i[2]  (
	.O(state_i_c[2]),
	.I0(state_c[2])
);
  INV sensor2_i_Z (
	.O(sensor2_i),
	.I0(sensor2_c)
);
  INV \state_i_Z[0]  (
	.O(state_i[0]),
	.I0(state[0])
);
  INV sensor1_i_Z (
	.O(sensor1_i),
	.I0(sensor1_c)
);
  AND2 G_58 (
	.O(N_74),
	.I0(state_i_c[2]),
	.I1(sensor2_c)
);
  AND2 G_59 (
	.O(N_75),
	.I0(sensor1_i),
	.I1(state_i[0])
);
  AND2 G_60 (
	.O(N_76),
	.I0(sensor1_c),
	.I1(state_i[0])
);
  AND2 green1_8_i_0 (
	.O(N_47_i_c),
	.I0(N_61),
	.I1(state_i_c[2])
);
  AND2 \nxstate_20_xor2_0[2]  (
	.O(N_79),
	.I0(N_62),
	.I1(yellow1_c_i)
);
  XOR2 G_62 (
	.O(N_60),
	.I0(state[1]),
	.I1(state_i[0])
);
  AND2 G_63 (
	.O(N_61_i_0),
	.I0(state[0]),
	.I1(state[1])
);
  AND2 yellow1_0_and2 (
	.O(yellow1_c),
	.I0(state_i_c[2]),
	.I1(N_61_i_0)
);
  AND2 yellow2_0_and2 (
	.O(yellow2_c),
	.I0(state_c[2]),
	.I1(N_61_i_0)
);
  AND2 \nxstate_20_0_and2_0[1]  (
	.O(N_69),
	.I0(N_74),
	.I1(N_75)
);
  AND2 \nxstate_20_0_and2[0]  (
	.O(N_70),
	.I0(state[1]),
	.I1(state_i[0])
);
  AND2 \nxstate_20_0_and2_0[0]  (
	.O(N_71),
	.I0(sensor2_i),
	.I1(N_75)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* traffic */