--
-- Written by Synplicity
-- Fri Oct 27 17:19:02 2000
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MACH_DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_DFF;

architecture beh of MACH_DFF is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CLK, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFFRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic);
end DFFRH;

architecture beh of DFFRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS1: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => UN1,
    S => NN_1,
    NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 xor I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity traffic is
port(
  clock :  in std_logic;
  reset :  in std_logic;
  sensor1 :  in std_logic;
  sensor2 :  in std_logic;
  red1 :  out std_logic;
  yellow1 :  out std_logic;
  green1 :  out std_logic;
  red2 :  out std_logic;
  yellow2 :  out std_logic;
  green2 :  out std_logic);
end traffic;

architecture beh of traffic is
  signal STATE : std_logic_vector(1 downto 0);
  signal NXSTATE_20 : std_logic_vector(2 downto 0);
  signal STATE_I : std_logic_vector(0 to 0);
  signal STATE_C : std_logic_vector(2 to 2);
  signal STATE_I_C : std_logic_vector(2 to 2);
  signal N_60 : std_logic ;
  signal N_61 : std_logic ;
  signal N_62 : std_logic ;
  signal N_68 : std_logic ;
  signal N_69 : std_logic ;
  signal N_70 : std_logic ;
  signal N_71 : std_logic ;
  signal N_72 : std_logic ;
  signal N_74 : std_logic ;
  signal N_75 : std_logic ;
  signal N_76 : std_logic ;
  signal SENSOR2_I : std_logic ;
  signal SENSOR1_I : std_logic ;
  signal CLOCK_C : std_logic ;
  signal RESET_C : std_logic ;
  signal SENSOR1_C : std_logic ;
  signal SENSOR2_C : std_logic ;
  signal YELLOW1_C : std_logic ;
  signal YELLOW2_C : std_logic ;
  signal YELLOW1_C_I : std_logic ;
  signal N_79 : std_logic ;
  signal N_70_I : std_logic ;
  signal N_71_I : std_logic ;
  signal N_72_I : std_logic ;
  signal N_81 : std_logic ;
  signal N_68_I : std_logic ;
  signal N_69_I : std_logic ;
  signal N_82 : std_logic ;
  signal N_62_I_C : std_logic ;
  signal N_47_I_C : std_logic ;
  signal N_61_I_0 : std_logic ;
  signal N_86 : std_logic ;
  signal N_87 : std_logic ;
  signal N_88 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DFFRH
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic  );
  end component;
  component IBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component OBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component AND2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
  component INV
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component XOR2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
begin
  \II_STATE[0]\: DFFRH port map (
    Q => STATE(0),
    D => NXSTATE_20(0),
    CLK => CLOCK_C,
    R => RESET_C);
  \II_STATE[1]\: DFFRH port map (
    Q => STATE(1),
    D => NXSTATE_20(1),
    CLK => CLOCK_C,
    R => RESET_C);
  \II_STATE[2]\: DFFRH port map (
    Q => STATE_C(2),
    D => NXSTATE_20(2),
    CLK => CLOCK_C,
    R => RESET_C);
  II_CLOCK: IBUF port map (
    O => CLOCK_C,
    I0 => clock);
  II_RESET: IBUF port map (
    O => RESET_C,
    I0 => reset);
  II_SENSOR1: IBUF port map (
    O => SENSOR1_C,
    I0 => sensor1);
  II_SENSOR2: IBUF port map (
    O => SENSOR2_C,
    I0 => sensor2);
  II_RED1: OBUF port map (
    O => red1,
    I0 => STATE_C(2));
  II_YELLOW1: OBUF port map (
    O => yellow1,
    I0 => YELLOW1_C);
  II_GREEN1: OBUF port map (
    O => green1,
    I0 => N_47_I_C);
  II_RED2: OBUF port map (
    O => red2,
    I0 => STATE_I_C(2));
  II_YELLOW2: OBUF port map (
    O => yellow2,
    I0 => YELLOW2_C);
  II_GREEN2: OBUF port map (
    O => green2,
    I0 => N_62_I_C);
  \II_NXSTATE_20_0_AND2_1.G_71\: AND2 port map (
    O => N_86,
    I0 => STATE_C(2),
    I1 => SENSOR2_I);
  \II_NXSTATE_20_0_1.G_72\: AND2 port map (
    O => N_87,
    I0 => N_68_I,
    I1 => N_69_I);
  \II_NXSTATE_20_0_0.G_73\: AND2 port map (
    O => N_88,
    I0 => N_70_I,
    I1 => N_72_I);
  II_GREEN2_8_I_0_OR2_I: INV port map (
    O => N_62,
    I0 => N_62_I_C);
  II_G_63_I: INV port map (
    O => N_61,
    I0 => N_61_I_0);
  II_YELLOW1_C_I: INV port map (
    O => YELLOW1_C_I,
    I0 => YELLOW1_C);
  \II_NXSTATE_20_XOR2_0_I[2]\: INV port map (
    O => NXSTATE_20(2),
    I0 => N_79);
  II_N_70_I: INV port map (
    O => N_70_I,
    I0 => N_70);
  II_N_71_I: INV port map (
    O => N_71_I,
    I0 => N_71);
  II_N_72_I: INV port map (
    O => N_72_I,
    I0 => N_72);
  \II_NXSTATE_20_0_I[0]\: INV port map (
    O => NXSTATE_20(0),
    I0 => N_81);
  II_N_68_I: INV port map (
    O => N_68_I,
    I0 => N_68);
  II_N_69_I: INV port map (
    O => N_69_I,
    I0 => N_69);
  \II_NXSTATE_20_0_I[1]\: INV port map (
    O => NXSTATE_20(1),
    I0 => N_82);
  \II_NXSTATE_20_0_AND2[1]\: AND2 port map (
    O => N_68,
    I0 => N_76,
    I1 => N_86);
  \II_NXSTATE_20_0[0]\: AND2 port map (
    O => N_81,
    I0 => N_71_I,
    I1 => N_88);
  \II_NXSTATE_20_0[1]\: AND2 port map (
    O => N_82,
    I0 => N_60,
    I1 => N_87);
  \II_NXSTATE_20_0_AND2_1[0]\: AND2 port map (
    O => N_72,
    I0 => N_74,
    I1 => N_76);
  II_GREEN2_8_I_0_OR2: AND2 port map (
    O => N_62_I_C,
    I0 => STATE_C(2),
    I1 => N_61);
  \II_STATE_I[2]\: INV port map (
    O => STATE_I_C(2),
    I0 => STATE_C(2));
  II_SENSOR2_I: INV port map (
    O => SENSOR2_I,
    I0 => SENSOR2_C);
  \II_STATE_I[0]\: INV port map (
    O => STATE_I(0),
    I0 => STATE(0));
  II_SENSOR1_I: INV port map (
    O => SENSOR1_I,
    I0 => SENSOR1_C);
  II_G_58: AND2 port map (
    O => N_74,
    I0 => STATE_I_C(2),
    I1 => SENSOR2_C);
  II_G_59: AND2 port map (
    O => N_75,
    I0 => SENSOR1_I,
    I1 => STATE_I(0));
  II_G_60: AND2 port map (
    O => N_76,
    I0 => SENSOR1_C,
    I1 => STATE_I(0));
  II_GREEN1_8_I_0: AND2 port map (
    O => N_47_I_C,
    I0 => N_61,
    I1 => STATE_I_C(2));
  \II_NXSTATE_20_XOR2_0[2]\: AND2 port map (
    O => N_79,
    I0 => N_62,
    I1 => YELLOW1_C_I);
  II_G_62: XOR2 port map (
    O => N_60,
    I0 => STATE(1),
    I1 => STATE_I(0));
  II_G_63: AND2 port map (
    O => N_61_I_0,
    I0 => STATE(0),
    I1 => STATE(1));
  II_YELLOW1_0_AND2: AND2 port map (
    O => YELLOW1_C,
    I0 => STATE_I_C(2),
    I1 => N_61_I_0);
  II_YELLOW2_0_AND2: AND2 port map (
    O => YELLOW2_C,
    I0 => STATE_C(2),
    I1 => N_61_I_0);
  \II_NXSTATE_20_0_AND2_0[1]\: AND2 port map (
    O => N_69,
    I0 => N_74,
    I1 => N_75);
  \II_NXSTATE_20_0_AND2[0]\: AND2 port map (
    O => N_70,
    I0 => STATE(1),
    I1 => STATE_I(0));
  \II_NXSTATE_20_0_AND2_0[0]\: AND2 port map (
    O => N_71,
    I0 => SENSOR2_I,
    I1 => N_75);
  GND <= '0';
  VCC <= '1';
end beh;