#-- Synplicity, Inc.
#-- Synplify version 5.3.2
#-- Project file C:\ispTOOLS\ispsys\examples\MACH_PAL\verilog\traffic\traffic.tc_
#-- Written on Fri Oct 27 17:19:01 2000

#device options
set_option -technology mach
set_option -part M4A3-32

#add_file options
add_file -verilog "c:/isptools/synplify/lib/cpld/lattice.v"
add_file -verilog "c:/isptools/ispsys/generic/verilog/synplify/generic.v"
add_file -verilog "traffic.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 0.000
set_option -fanin_limit 20
set_option -max_terms_per_macrocell 16
set_option -map_logic false
set_option -area_delay_percent 0
set_option -top_module traffic

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
set_option -mti_root ""

#set result format/file last
project -result_file "traffic.edi"