| Name: sn7485.cmd
|Test script for Verilog SN74LS85 4-Bit Magnitude Comparator module sn7485
| Written by: Jianjian Song, October 2000 
|========================SETUP the Stimulus environment==============
|delete any existing waveforms in the window
|
delete_signals
|--------------------------
| Clear the the file sim_out.out for capturing output directed
| to this file later. This file can be used by Multiple commands
| like BREAK and PRINT to output simulation information.
|
clpr sim_out.out
|--------------------------
| Restart to time zero
|
restart
| set up input vector, which will be displayed automatically
vector INPUT_VEC  IAGB IALB IAEB A[3:0] B[3:0]
| display these signals in waveform window
watch QAGB
watch QALB
watch QAEB
|--------------------------
| set the clock step size
stepsize 50.0ns
| Assign a value to input vector and clock once with cycle
assign INPUT_VEC 0
cycle
| A3 > B3
assign INPUT_VEC 085\H
cycle
| A3 < B3
assign INPUT_VEC 339\H
cycle
| A3 < B3
assign INPUT_VEC 3AC\H
cycle
| A3==B3, A2>B2
assign INPUT_VEC 01101010001
cycle
| A3==B3, A2<B2
assign INPUT_VEC 01100010111
cycle
| A3==B3, A2==B2, A1>B1
assign INPUT_VEC 11100100001
cycle
| A3==B3, A2==B2, A1<B1
assign INPUT_VEC 10101010111
cycle
| A3==B3, A2==B2, A1==B1, A0>B0
assign INPUT_VEC 10101010100
cycle
| A3==B3, A2==B2, A1==B1, A0<B0
assign INPUT_VEC 10011101111
cycle
| A==B IAGB=1 IALB=0 IAEB=0
assign INPUT_VEC 499\H
cycle
| A==B IAGB=0 IALB=1 IAEB=0
assign INPUT_VEC 2FF\H
cycle
| A==B IAGB=0 IALB=0 IAEB=1
assign INPUT_VEC 1FF\H
cycle
| A==B IAGB=1 IALB=1 IAEB=1
assign INPUT_VEC 700\H
cycle
| A==B IAGB=1 IALB=1 IAEB=0
assign INPUT_VEC 6CC\H
cycle
| A==B IAGB=0 IALB=0 IAEB=0
assign INPUT_VEC 0FF\H
cycle
| save results in a file
print sim_out.out