// File name	: shiftreg.v
// shift register
// Jianjian Song, EC333 Fall 2000
module shiftreg(D,Q,RESET,CLK) ;
// serial-in parallel-out shift register with reset
parameter	LENGTH = 4;
input			D, RESET, CLK;
output 	[LENGTH:1]	Q;
reg	Q;
always @ (posedge CLK or posedge RESET)
	if(RESET==1)	Q = 0;
	else		Q = {Q[LENGTH-1:1],D};
endmodule