| Name: shiftreg.cmd
|Test script for Verilog shift register with Xilinx
| Written by: Jianjian Song, 1 Nov 2000 
|========================SETUP the Stimulus environment==============
|delete any existing waveforms in the window
|
delete_signals
|
clpr sim_out.out
|--------------------------
| Restart to time zero
|
restart
|vector input_vec CLK D RESET
| display these signals in waveform window
|vector input_vec D RESET
watch CLK
watch RESET
watch D
watch Q[4:1]
|--------------------------
| set the clock step size
stepsize 50.0ns
clock CLK 0 1	| define 100 ns period clock
| Assign a value to input vector and clock once with cycle
assign RESET 1\b
assign D 1\b
cycle
assign RESET 0\b
assign D 0\b
cycle
assign RESET 0\b
assign D 1\b
cycle
assign RESET 0\b
assign D 1\b
cycle
assign RESET 0\b
assign D 0\b
cycle
assign RESET 0\b
assign D 0\b
cycle
assign RESET 0\b
assign D 1\b
cycle
assign RESET 0\b
assign D 1\b
cycle
assign RESET 0\b
assign D 1\b
cycle
assign RESET 1\b
assign D 1\b
cycle
|print sim_out.out