MODULE SHIFTREG
" TOOL:     ispDesignExpert
" DATE:     2000.10.29 
" TITLE:    ispDesignExpert
" MODULE:   SHIFTREG
" DESIGN:   SHIFTREG
" FILENAME: shiftreg.abv
" PROJECT:  simple
" VERSION:  8.1

" Inputs
    D pin;
    RESET pin;
    CLK pin;


" Outputs
    Q_1_ pin;
    Q_2_ pin;
    Q_3_ pin;
    Q_4_ pin;

Test_vectors
([D,RESET,CLK] -> [Q_1_,Q_2_,Q_3_,Q_4_])
	[1,1,.C.] -> [0,0,0,0];
	[1,0,.C.] -> [1,0,0,0];
	[0,0,.C.] -> [0,1,0,0];
	[0,0,.C.] -> [0,0,1,0];
	[1,0,.C.] -> [1,0,0,1];
	[1,0,.C.] -> [1,1,0,0];
	[0,0,.C.] -> [0,1,1,0];
	[0,1,.C.] -> [0,0,0,0];
END SHIFTREG